d3cd0071a8
Storage technologies like FRAM have no "write pages", the whole chip can be written within one SPI transfer. For these chips, the page size can be set equal to the device size. Currently available devices are already bigger than 64 kiB. Signed-off-by: Christian Eggers <ceggers@arri.de> Link: https://lore.kernel.org/r/20200727111218.26926-1-ceggers@arri.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef __LINUX_SPI_EEPROM_H
|
|
#define __LINUX_SPI_EEPROM_H
|
|
|
|
#include <linux/memory.h>
|
|
|
|
/*
|
|
* Put one of these structures in platform_data for SPI EEPROMS handled
|
|
* by the "at25" driver. On SPI, most EEPROMS understand the same core
|
|
* command set. If you need to support EEPROMs that don't yet fit, add
|
|
* flags to support those protocol options. These values all come from
|
|
* the chip datasheets.
|
|
*/
|
|
struct spi_eeprom {
|
|
u32 byte_len;
|
|
char name[10];
|
|
u32 page_size; /* for writes */
|
|
u16 flags;
|
|
#define EE_ADDR1 0x0001 /* 8 bit addrs */
|
|
#define EE_ADDR2 0x0002 /* 16 bit addrs */
|
|
#define EE_ADDR3 0x0004 /* 24 bit addrs */
|
|
#define EE_READONLY 0x0008 /* disallow writes */
|
|
|
|
/*
|
|
* Certain EEPROMS have a size that is larger than the number of address
|
|
* bytes would allow (e.g. like M95040 from ST that has 512 Byte size
|
|
* but uses only one address byte (A0 to A7) for addressing.) For
|
|
* the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
|
|
* is used. This instruction bit is normally defined as don't care for
|
|
* other AT25 like chips.
|
|
*/
|
|
#define EE_INSTR_BIT3_IS_ADDR 0x0010
|
|
|
|
void *context;
|
|
};
|
|
|
|
#endif /* __LINUX_SPI_EEPROM_H */
|