drm/amd/display: Skip modeset for front porch change
[Why] A seamless transition between modes can be performed if the new incoming mode has the same timing parameters as the optimized mode on a display with a variable vtotal min/max. Smooth video playback usecases can be enabled with this seamless transition by switching to a new mode which has a refresh rate matching the video. [How] Skip full modeset if userspace requested a compatible freesync mode which only differs in the front porch timing from the current mode. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai
Alex Deucher
parent
d10cd527f5
commit
6f59f229f8
@ -213,6 +213,9 @@ static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
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static const struct drm_format_info *
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amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
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static bool
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is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
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struct drm_crtc_state *new_crtc_state);
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/*
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* dm_vblank_get_counter
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*
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@ -336,6 +339,17 @@ static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
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dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
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}
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static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
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struct dm_crtc_state *new_state)
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{
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if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
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return true;
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else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
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return true;
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else
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return false;
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}
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/**
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* dm_pflip_high_irq() - Handle pageflip interrupt
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* @interrupt_params: ignored
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@ -4993,19 +5007,16 @@ static void fill_stream_properties_from_drm_display_mode(
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timing_out->hdmi_vic = hv_frame.vic;
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}
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timing_out->h_addressable = mode_in->crtc_hdisplay;
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timing_out->h_total = mode_in->crtc_htotal;
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timing_out->h_sync_width =
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mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
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timing_out->h_front_porch =
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mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
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timing_out->v_total = mode_in->crtc_vtotal;
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timing_out->v_addressable = mode_in->crtc_vdisplay;
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timing_out->v_front_porch =
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mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
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timing_out->v_sync_width =
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mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
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timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
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timing_out->h_addressable = mode_in->hdisplay;
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timing_out->h_total = mode_in->htotal;
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timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
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timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
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timing_out->v_total = mode_in->vtotal;
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timing_out->v_addressable = mode_in->vdisplay;
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timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
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timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
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timing_out->pix_clk_100hz = mode_in->clock * 10;
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timing_out->aspect_ratio = get_aspect_ratio(mode_in);
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stream->output_color_space = get_output_color_space(timing_out);
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@ -5225,6 +5236,33 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
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return m_pref;
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}
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static bool is_freesync_video_mode(struct drm_display_mode *mode,
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struct amdgpu_dm_connector *aconnector)
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{
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struct drm_display_mode *high_mode;
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int timing_diff;
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high_mode = get_highest_refresh_rate_mode(aconnector, false);
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if (!high_mode || !mode)
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return false;
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timing_diff = high_mode->vtotal - mode->vtotal;
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if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
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high_mode->hdisplay != mode->hdisplay ||
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high_mode->vdisplay != mode->vdisplay ||
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high_mode->hsync_start != mode->hsync_start ||
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high_mode->hsync_end != mode->hsync_end ||
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high_mode->htotal != mode->htotal ||
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high_mode->hskew != mode->hskew ||
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high_mode->vscan != mode->vscan ||
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high_mode->vsync_start - mode->vsync_start != timing_diff ||
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high_mode->vsync_end - mode->vsync_end != timing_diff)
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return false;
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else
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return true;
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}
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static struct dc_stream_state *
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create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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const struct drm_display_mode *drm_mode,
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@ -5238,8 +5276,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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dm_state ? &dm_state->base : NULL;
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struct dc_stream_state *stream = NULL;
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struct drm_display_mode mode = *drm_mode;
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struct drm_display_mode saved_mode;
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struct drm_display_mode *freesync_mode = NULL;
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bool native_mode_found = false;
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bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
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bool recalculate_timing = dm_state ? (dm_state->scaling != RMX_OFF) : false;
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int mode_refresh;
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int preferred_refresh = 0;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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@ -5247,6 +5287,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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uint32_t link_bandwidth_kbps;
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#endif
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struct dc_sink *sink = NULL;
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memset(&saved_mode, 0, sizeof(saved_mode));
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if (aconnector == NULL) {
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DRM_ERROR("aconnector is NULL!\n");
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return stream;
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@ -5299,25 +5342,38 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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*/
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DRM_DEBUG_DRIVER("No preferred mode found\n");
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} else {
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decide_crtc_timing_for_drm_display_mode(
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recalculate_timing |= amdgpu_freesync_vid_mode &&
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is_freesync_video_mode(&mode, aconnector);
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if (recalculate_timing) {
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freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
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saved_mode = mode;
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mode = *freesync_mode;
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} else {
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decide_crtc_timing_for_drm_display_mode(
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&mode, preferred_mode,
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dm_state ? (dm_state->scaling != RMX_OFF) : false);
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}
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preferred_refresh = drm_mode_vrefresh(preferred_mode);
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}
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if (!dm_state)
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if (recalculate_timing)
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drm_mode_set_crtcinfo(&saved_mode, 0);
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else
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drm_mode_set_crtcinfo(&mode, 0);
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/*
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/*
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* If scaling is enabled and refresh rate didn't change
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* we copy the vic and polarities of the old timings
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*/
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if (!scale || mode_refresh != preferred_refresh)
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fill_stream_properties_from_drm_display_mode(stream,
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&mode, &aconnector->base, con_state, NULL, requested_bpc);
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if (!recalculate_timing || mode_refresh != preferred_refresh)
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fill_stream_properties_from_drm_display_mode(
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stream, &mode, &aconnector->base, con_state, NULL,
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requested_bpc);
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else
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fill_stream_properties_from_drm_display_mode(stream,
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&mode, &aconnector->base, con_state, old_stream, requested_bpc);
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fill_stream_properties_from_drm_display_mode(
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stream, &mode, &aconnector->base, con_state, old_stream,
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requested_bpc);
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stream->timing.flags.DSC = 0;
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@ -7802,9 +7858,22 @@ static void update_stream_irq_parameters(
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if (new_crtc_state->vrr_supported &&
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config.min_refresh_in_uhz &&
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config.max_refresh_in_uhz) {
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config.state = new_crtc_state->base.vrr_enabled ?
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VRR_STATE_ACTIVE_VARIABLE :
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VRR_STATE_INACTIVE;
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/*
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* if freesync compatible mode was set, config.state will be set
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* in atomic check
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*/
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if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
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(!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
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new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
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vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
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vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
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vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
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vrr_params.state = VRR_STATE_ACTIVE_FIXED;
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} else {
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config.state = new_crtc_state->base.vrr_enabled ?
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VRR_STATE_ACTIVE_VARIABLE :
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VRR_STATE_INACTIVE;
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}
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} else {
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config.state = VRR_STATE_UNSUPPORTED;
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}
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@ -8125,8 +8194,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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* re-adjust the min/max bounds now that DC doesn't handle this
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* as part of commit.
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*/
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if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
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amdgpu_dm_vrr_active(acrtc_state)) {
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if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
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spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
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dc_stream_adjust_vmin_vmax(
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dm->dc, acrtc_state->stream,
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@ -8411,6 +8479,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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/* i.e. reset mode */
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if (dm_old_crtc_state->stream)
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remove_stream(adev, acrtc, dm_old_crtc_state->stream);
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mode_set_reset_required = true;
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}
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} /* for_each_crtc_in_state() */
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@ -8809,6 +8878,7 @@ static void get_freesync_config_for_crtc(
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to_amdgpu_dm_connector(new_con_state->base.connector);
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struct drm_display_mode *mode = &new_crtc_state->base.mode;
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int vrefresh = drm_mode_vrefresh(mode);
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bool fs_vid_mode = false;
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new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
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vrefresh >= aconnector->min_vfreq &&
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@ -8816,17 +8886,24 @@ static void get_freesync_config_for_crtc(
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if (new_crtc_state->vrr_supported) {
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new_crtc_state->stream->ignore_msa_timing_param = true;
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config.state = new_crtc_state->base.vrr_enabled ?
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VRR_STATE_ACTIVE_VARIABLE :
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VRR_STATE_INACTIVE;
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config.min_refresh_in_uhz =
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aconnector->min_vfreq * 1000000;
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config.max_refresh_in_uhz =
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aconnector->max_vfreq * 1000000;
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fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
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config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
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config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
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config.vsif_supported = true;
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config.btr = true;
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}
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if (fs_vid_mode) {
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config.state = VRR_STATE_ACTIVE_FIXED;
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config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
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goto out;
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} else if (new_crtc_state->base.vrr_enabled) {
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config.state = VRR_STATE_ACTIVE_VARIABLE;
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} else {
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config.state = VRR_STATE_INACTIVE;
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}
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}
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out:
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new_crtc_state->freesync_config = config;
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}
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@ -8839,6 +8916,50 @@ static void reset_freesync_config_for_crtc(
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sizeof(new_crtc_state->vrr_infopacket));
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}
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static bool
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is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
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struct drm_crtc_state *new_crtc_state)
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{
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struct drm_display_mode old_mode, new_mode;
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if (!old_crtc_state || !new_crtc_state)
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return false;
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old_mode = old_crtc_state->mode;
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new_mode = new_crtc_state->mode;
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if (old_mode.clock == new_mode.clock &&
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old_mode.hdisplay == new_mode.hdisplay &&
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old_mode.vdisplay == new_mode.vdisplay &&
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old_mode.htotal == new_mode.htotal &&
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old_mode.vtotal != new_mode.vtotal &&
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old_mode.hsync_start == new_mode.hsync_start &&
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old_mode.vsync_start != new_mode.vsync_start &&
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old_mode.hsync_end == new_mode.hsync_end &&
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old_mode.vsync_end != new_mode.vsync_end &&
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old_mode.hskew == new_mode.hskew &&
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old_mode.vscan == new_mode.vscan &&
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(old_mode.vsync_end - old_mode.vsync_start) ==
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(new_mode.vsync_end - new_mode.vsync_start))
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return true;
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return false;
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}
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static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
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uint64_t num, den, res;
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struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
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dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
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num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
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den = (unsigned long long)new_crtc_state->mode.htotal *
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(unsigned long long)new_crtc_state->mode.vtotal;
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res = div_u64(num, den);
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dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
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}
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static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
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struct drm_atomic_state *state,
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struct drm_crtc *crtc,
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@ -8929,6 +9050,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
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* TODO: Refactor this function to allow this check to work
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* in all conditions.
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*/
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if (amdgpu_freesync_vid_mode &&
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dm_new_crtc_state->stream &&
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is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
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goto skip_modeset;
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if (dm_new_crtc_state->stream &&
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dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
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dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
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@ -8960,6 +9086,24 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
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if (!dm_old_crtc_state->stream)
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goto skip_modeset;
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if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
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is_timing_unchanged_for_freesync(new_crtc_state,
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old_crtc_state)) {
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new_crtc_state->mode_changed = false;
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DRM_DEBUG_DRIVER(
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"Mode change not required for front porch change, "
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"setting mode_changed to %d",
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new_crtc_state->mode_changed);
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set_freesync_fixed_config(dm_new_crtc_state);
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goto skip_modeset;
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} else if (amdgpu_freesync_vid_mode && aconnector &&
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is_freesync_video_mode(&new_crtc_state->mode,
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aconnector)) {
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set_freesync_fixed_config(dm_new_crtc_state);
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}
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ret = dm_atomic_get_state(state, &dm_state);
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if (ret)
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goto fail;
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