PCI: Fix kernel-doc formatting

Fix kernel-doc formatting throughout drivers/pci and related include files.
No change to functionality intended.

Check for warnings:

  $ find include drivers/pci -type f -path "*pci*.[ch]" | xargs scripts/kernel-doc -none

[bhelgaas: squashed to one commit]
Link: https://lore.kernel.org/r/20210509030237.368540-1-kw@linux.com
Link: https://lore.kernel.org/r/20210703151306.1922450-1-kw@linux.com
Link: https://lore.kernel.org/r/20210703151306.1922450-2-kw@linux.com
Link: https://lore.kernel.org/r/20210703151306.1922450-3-kw@linux.com
Link: https://lore.kernel.org/r/20210703151306.1922450-4-kw@linux.com
Link: https://lore.kernel.org/r/20210703151306.1922450-5-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Krzysztof Wilczyński 2021-07-03 15:13:02 +00:00 committed by Bjorn Helgaas
parent 6efb943b86
commit 347269c113
14 changed files with 52 additions and 33 deletions

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@ -263,9 +263,12 @@ struct cdns_pcie_ops {
* struct cdns_pcie - private data for Cadence PCIe controller drivers
* @reg_base: IO mapped register base
* @mem_res: start/end offsets in the physical system memory to map PCI accesses
* @dev: PCIe controller
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
* @bus: In Root Complex mode, the bus number
* @ops: Platform specific ops to control various inputs from Cadence PCIe
* @phy_count: number of supported PHY devices
* @phy: list of pointers to specific PHY control blocks
* @link: list of pointers to corresponding device link representations
* @ops: Platform-specific ops to control various inputs from Cadence PCIe
* wrapper
*/
struct cdns_pcie {

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@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/**
/*
* APM X-Gene PCIe Driver
*
* Copyright (c) 2014 Applied Micro Circuits Corporation.

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@ -49,7 +49,7 @@ enum iproc_msi_reg {
struct iproc_msi;
/**
* iProc MSI group
* struct iproc_msi_grp - iProc MSI group
*
* One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
* event queue.
@ -65,7 +65,7 @@ struct iproc_msi_grp {
};
/**
* iProc event queue based MSI
* struct iproc_msi - iProc event queue based MSI
*
* Only meant to be used on platforms without MSI support integrated into the
* GIC.

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@ -89,8 +89,8 @@
#define IPROC_PCIE_REG_INVALID 0xffff
/**
* iProc PCIe outbound mapping controller specific parameters
*
* struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
* parameters
* @window_sizes: list of supported outbound mapping window sizes in MB
* @nr_sizes: number of supported outbound mapping window sizes
*/
@ -136,22 +136,20 @@ static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
};
/**
* iProc PCIe inbound mapping type
* enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
* @IPROC_PCIE_IB_MAP_MEM: DDR memory
* @IPROC_PCIE_IB_MAP_IO: device I/O memory
* @IPROC_PCIE_IB_MAP_INVALID: invalid or unused
*/
enum iproc_pcie_ib_map_type {
/* for DDR memory */
IPROC_PCIE_IB_MAP_MEM = 0,
/* for device I/O memory */
IPROC_PCIE_IB_MAP_IO,
/* invalid or unused */
IPROC_PCIE_IB_MAP_INVALID
};
/**
* iProc PCIe inbound mapping controller specific parameters
*
* struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
* parameters
* @type: inbound mapping region type
* @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or
* SZ_1G
@ -437,7 +435,7 @@ static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
writel(val, pcie->base + offset);
}
/**
/*
* APB error forwarding can be disabled during access of configuration
* registers of the endpoint device, to prevent unsupported requests
* (typically seen during enumeration with multi-function devices) from
@ -619,7 +617,7 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
}
/**
/*
* Note access to the configuration registers are protected at the higher layer
* by 'pci_lock' in drivers/pci/access.c
*/
@ -897,7 +895,7 @@ static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
return 0;
}
/**
/*
* Some iProc SoCs require the SW to configure the outbound address mapping
*
* Outbound address translation:

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@ -7,7 +7,13 @@
#define _PCIE_IPROC_H
/**
* iProc PCIe interface type
* enum iproc_pcie_type - iProc PCIe interface type
* @IPROC_PCIE_PAXB_BCMA: BCMA-based host controllers
* @IPROC_PCIE_PAXB: PAXB-based host controllers for
* NS, NSP, Cygnus, NS2, and Pegasus SOCs
* @IPROC_PCIE_PAXB_V2: PAXB-based host controllers for Stingray SoCs
* @IPROC_PCIE_PAXC: PAXC-based host controllers
* @IPROC_PCIE_PAXC_V2: PAXC-based host controllers (second generation)
*
* PAXB is the wrapper used in root complex that can be connected to an
* external endpoint device.
@ -24,7 +30,7 @@ enum iproc_pcie_type {
};
/**
* iProc PCIe outbound mapping
* struct iproc_pcie_ob - iProc PCIe outbound mapping
* @axi_offset: offset from the AXI address to the internal address used by
* the iProc PCIe core
* @nr_windows: total number of supported outbound mapping windows
@ -35,7 +41,7 @@ struct iproc_pcie_ob {
};
/**
* iProc PCIe inbound mapping
* struct iproc_pcie_ib - iProc PCIe inbound mapping
* @nr_regions: total number of supported inbound mapping regions
*/
struct iproc_pcie_ib {
@ -47,13 +53,13 @@ struct iproc_pcie_ib_map;
struct iproc_msi;
/**
* iProc PCIe device
*
* struct iproc_pcie - iProc PCIe device
* @dev: pointer to device data structure
* @type: iProc PCIe interface type
* @reg_offsets: register offsets
* @base: PCIe host controller I/O register base
* @base_addr: PCIe host controller register base physical address
* @mem: host bridge memory window resource
* @phy: optional PHY device that controls the Serdes
* @map_irq: function callback to map interrupts
* @ep_is_internal: indicates an internal emulated endpoint device is connected

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@ -296,9 +296,10 @@ static int ctrl_slot_cleanup(struct controller *ctrl)
*
* Won't work for more than one PCI-PCI bridge in a slot.
*
* @bus_num - bus number of PCI device
* @dev_num - device number of PCI device
* @slot - Pointer to u8 where slot number will be returned
* @bus: pointer to the PCI bus structure
* @bus_num: bus number of PCI device
* @dev_num: device number of PCI device
* @slot: Pointer to u8 where slot number will be returned
*
* Output: SUCCESS or FAILURE
*/

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@ -1877,7 +1877,7 @@ static void interrupt_event_handler(struct controller *ctrl)
/**
* cpqhp_pushbutton_thread - handle pushbutton events
* @slot: target slot (struct)
* @t: pointer to struct timer_list which holds all timer-related callbacks
*
* Scheduled procedure to handle blocking stuff for the pushbuttons.
* Handles all pending events and exits.

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@ -47,6 +47,9 @@ extern int pciehp_poll_time;
* struct controller - PCIe hotplug controller
* @pcie: pointer to the controller's PCIe port service device
* @slot_cap: cached copy of the Slot Capabilities register
* @inband_presence_disabled: In-Band Presence Detect Disable supported by
* controller and disabled per spec recommendation (PCIe r5.0, appendix I
* implementation note)
* @slot_ctrl: cached copy of the Slot Control register
* @ctrl_lock: serializes writes to the Slot Control register
* @cmd_started: jiffies when the Slot Control register was last written;

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@ -324,8 +324,8 @@ struct pci_sriov {
/**
* pci_dev_set_io_state - Set the new error state if possible.
*
* @dev - pci device to set new error_state
* @new - the state we want dev to be in
* @dev: PCI device to set new error_state
* @new: the state we want dev to be in
*
* Must be called with device_lock held.
*

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@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/**
/*
* PCI Endpoint ConfigFS header file
*
* Copyright (C) 2017 Texas Instruments

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@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/**
/*
* PCI Endpoint *Controller* (EPC) header file
*
* Copyright (C) 2017 Texas Instruments
@ -58,6 +58,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type)
* @map_msi_irq: ops to map physical address to MSI address and return MSI data
* @start: ops to start the PCI link
* @stop: ops to stop the PCI link
* @get_features: ops to get the features supported by the EPC
* @owner: the module owner containing the ops
*/
struct pci_epc_ops {
@ -150,6 +151,8 @@ struct pci_epc {
/**
* struct pci_epc_features - features supported by a EPC device per function
* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
* @core_init_notifier: indicate cores that can notify about their availability
* for initialization
* @msi_capable: indicate if the endpoint function has MSI capability
* @msix_capable: indicate if the endpoint function has MSI-X capability
* @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver

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@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/**
/*
* PCI Endpoint *Function* (EPF) header file
*
* Copyright (C) 2017 Texas Instruments
@ -102,6 +102,8 @@ struct pci_epf_driver {
* @phys_addr: physical address that should be mapped to the BAR
* @addr: virtual address corresponding to the @phys_addr
* @size: the size of the address space present in BAR
* @barno: BAR number
* @flags: flags that are set for the BAR
*/
struct pci_epf_bar {
dma_addr_t phys_addr;
@ -118,6 +120,7 @@ struct pci_epf_bar {
* @header: represents standard configuration header
* @bar: represents the BAR of EPF device
* @msi_interrupts: number of MSI interrupts required by this function
* @msix_interrupts: number of MSI-X interrupts required by this function
* @func_no: unique function number within this endpoint device
* @epc: the EPC device to which this EPF device is bound
* @driver: the EPF driver to which this EPF device is bound

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@ -50,6 +50,8 @@ struct hotplug_slot_ops {
/**
* struct hotplug_slot - used to register a physical slot with the hotplug pci core
* @ops: pointer to the &struct hotplug_slot_ops to be used for this slot
* @slot_list: internal list used to track hotplug PCI slots
* @pci_slot: represents a physical slot
* @owner: The module owner of this structure
* @mod_name: The module name (KBUILD_MODNAME) of this structure
*/

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@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/**
/*
* pcitest.h - PCI test uapi defines
*
* Copyright (C) 2017 Texas Instruments