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https://github.com/edk2-porting/linux-next.git
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5a61640e32
emulate_step() tests are failing if VSX is not supported or disabled. emulate_step_test: lxvd2x : FAIL emulate_step_test: stxvd2x : FAIL If !CPU_FTR_VSX, emulate_step() failure is expected and testcase should PASS with a valid justification. After patch: emulate_step_test: lxvd2x : PASS (!CPU_FTR_VSX) emulate_step_test: stxvd2x : PASS (!CPU_FTR_VSX) Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
444 lines
9.5 KiB
C
444 lines
9.5 KiB
C
/*
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* Simple sanity test for emulate_step load/store instructions.
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*
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* Copyright IBM Corp. 2016
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#define pr_fmt(fmt) "emulate_step_test: " fmt
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#include <linux/ptrace.h>
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#include <asm/sstep.h>
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#include <asm/ppc-opcode.h>
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#define IMM_L(i) ((uintptr_t)(i) & 0xffff)
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/*
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* Defined with TEST_ prefix so it does not conflict with other
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* definitions.
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*/
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#define TEST_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | \
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___PPC_RA(base) | IMM_L(i))
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#define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \
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___PPC_RA(base) | IMM_L(i))
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#define TEST_LWZX(t, a, b) (PPC_INST_LWZX | ___PPC_RT(t) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | \
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___PPC_RA(base) | ((i) & 0xfffc))
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#define TEST_LDARX(t, a, b, eh) (PPC_INST_LDARX | ___PPC_RT(t) | \
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___PPC_RA(a) | ___PPC_RB(b) | \
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__PPC_EH(eh))
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#define TEST_STDCX(s, a, b) (PPC_INST_STDCX | ___PPC_RS(s) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_LFSX(t, a, b) (PPC_INST_LFSX | ___PPC_RT(t) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_STFSX(s, a, b) (PPC_INST_STFSX | ___PPC_RS(s) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_LFDX(t, a, b) (PPC_INST_LFDX | ___PPC_RT(t) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_STFDX(s, a, b) (PPC_INST_STFDX | ___PPC_RS(s) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_LVX(t, a, b) (PPC_INST_LVX | ___PPC_RT(t) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_STVX(s, a, b) (PPC_INST_STVX | ___PPC_RS(s) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define TEST_LXVD2X(s, a, b) (PPC_INST_LXVD2X | VSX_XX1((s), R##a, R##b))
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#define TEST_STXVD2X(s, a, b) (PPC_INST_STXVD2X | VSX_XX1((s), R##a, R##b))
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static void __init init_pt_regs(struct pt_regs *regs)
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{
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static unsigned long msr;
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static bool msr_cached;
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memset(regs, 0, sizeof(struct pt_regs));
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if (likely(msr_cached)) {
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regs->msr = msr;
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return;
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}
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asm volatile("mfmsr %0" : "=r"(regs->msr));
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regs->msr |= MSR_FP;
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regs->msr |= MSR_VEC;
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regs->msr |= MSR_VSX;
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msr = regs->msr;
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msr_cached = true;
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}
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static void __init show_result(char *ins, char *result)
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{
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pr_info("%-14s : %s\n", ins, result);
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}
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static void __init test_ld(void)
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{
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struct pt_regs regs;
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unsigned long a = 0x23;
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int stepped = -1;
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init_pt_regs(®s);
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regs.gpr[3] = (unsigned long) &a;
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/* ld r5, 0(r3) */
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stepped = emulate_step(®s, TEST_LD(5, 3, 0));
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if (stepped == 1 && regs.gpr[5] == a)
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show_result("ld", "PASS");
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else
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show_result("ld", "FAIL");
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}
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static void __init test_lwz(void)
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{
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struct pt_regs regs;
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unsigned int a = 0x4545;
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int stepped = -1;
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init_pt_regs(®s);
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regs.gpr[3] = (unsigned long) &a;
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/* lwz r5, 0(r3) */
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stepped = emulate_step(®s, TEST_LWZ(5, 3, 0));
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if (stepped == 1 && regs.gpr[5] == a)
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show_result("lwz", "PASS");
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else
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show_result("lwz", "FAIL");
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}
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static void __init test_lwzx(void)
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{
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struct pt_regs regs;
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unsigned int a[3] = {0x0, 0x0, 0x1234};
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int stepped = -1;
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init_pt_regs(®s);
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regs.gpr[3] = (unsigned long) a;
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regs.gpr[4] = 8;
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regs.gpr[5] = 0x8765;
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/* lwzx r5, r3, r4 */
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stepped = emulate_step(®s, TEST_LWZX(5, 3, 4));
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if (stepped == 1 && regs.gpr[5] == a[2])
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show_result("lwzx", "PASS");
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else
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show_result("lwzx", "FAIL");
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}
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static void __init test_std(void)
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{
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struct pt_regs regs;
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unsigned long a = 0x1234;
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int stepped = -1;
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init_pt_regs(®s);
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regs.gpr[3] = (unsigned long) &a;
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regs.gpr[5] = 0x5678;
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/* std r5, 0(r3) */
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stepped = emulate_step(®s, TEST_STD(5, 3, 0));
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if (stepped == 1 || regs.gpr[5] == a)
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show_result("std", "PASS");
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else
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show_result("std", "FAIL");
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}
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static void __init test_ldarx_stdcx(void)
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{
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struct pt_regs regs;
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unsigned long a = 0x1234;
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int stepped = -1;
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unsigned long cr0_eq = 0x1 << 29; /* eq bit of CR0 */
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init_pt_regs(®s);
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asm volatile("mfcr %0" : "=r"(regs.ccr));
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/*** ldarx ***/
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regs.gpr[3] = (unsigned long) &a;
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regs.gpr[4] = 0;
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regs.gpr[5] = 0x5678;
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/* ldarx r5, r3, r4, 0 */
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stepped = emulate_step(®s, TEST_LDARX(5, 3, 4, 0));
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/*
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* Don't touch 'a' here. Touching 'a' can do Load/store
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* of 'a' which result in failure of subsequent stdcx.
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* Instead, use hardcoded value for comparison.
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*/
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if (stepped <= 0 || regs.gpr[5] != 0x1234) {
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show_result("ldarx / stdcx.", "FAIL (ldarx)");
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return;
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}
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/*** stdcx. ***/
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regs.gpr[5] = 0x9ABC;
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/* stdcx. r5, r3, r4 */
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stepped = emulate_step(®s, TEST_STDCX(5, 3, 4));
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/*
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* Two possible scenarios that indicates successful emulation
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* of stdcx. :
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* 1. Reservation is active and store is performed. In this
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* case cr0.eq bit will be set to 1.
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* 2. Reservation is not active and store is not performed.
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* In this case cr0.eq bit will be set to 0.
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*/
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if (stepped == 1 && ((regs.gpr[5] == a && (regs.ccr & cr0_eq))
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|| (regs.gpr[5] != a && !(regs.ccr & cr0_eq))))
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show_result("ldarx / stdcx.", "PASS");
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else
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show_result("ldarx / stdcx.", "FAIL (stdcx.)");
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}
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#ifdef CONFIG_PPC_FPU
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static void __init test_lfsx_stfsx(void)
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{
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struct pt_regs regs;
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union {
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float a;
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int b;
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} c;
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int cached_b;
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int stepped = -1;
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init_pt_regs(®s);
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/*** lfsx ***/
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c.a = 123.45;
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cached_b = c.b;
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regs.gpr[3] = (unsigned long) &c.a;
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regs.gpr[4] = 0;
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/* lfsx frt10, r3, r4 */
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stepped = emulate_step(®s, TEST_LFSX(10, 3, 4));
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if (stepped == 1)
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show_result("lfsx", "PASS");
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else
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show_result("lfsx", "FAIL");
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/*** stfsx ***/
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c.a = 678.91;
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/* stfsx frs10, r3, r4 */
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stepped = emulate_step(®s, TEST_STFSX(10, 3, 4));
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if (stepped == 1 && c.b == cached_b)
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show_result("stfsx", "PASS");
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else
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show_result("stfsx", "FAIL");
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}
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static void __init test_lfdx_stfdx(void)
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{
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struct pt_regs regs;
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union {
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double a;
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long b;
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} c;
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long cached_b;
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int stepped = -1;
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init_pt_regs(®s);
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/*** lfdx ***/
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c.a = 123456.78;
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cached_b = c.b;
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regs.gpr[3] = (unsigned long) &c.a;
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regs.gpr[4] = 0;
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/* lfdx frt10, r3, r4 */
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stepped = emulate_step(®s, TEST_LFDX(10, 3, 4));
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if (stepped == 1)
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show_result("lfdx", "PASS");
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else
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show_result("lfdx", "FAIL");
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/*** stfdx ***/
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c.a = 987654.32;
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/* stfdx frs10, r3, r4 */
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stepped = emulate_step(®s, TEST_STFDX(10, 3, 4));
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if (stepped == 1 && c.b == cached_b)
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show_result("stfdx", "PASS");
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else
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show_result("stfdx", "FAIL");
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}
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#else
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static void __init test_lfsx_stfsx(void)
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{
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show_result("lfsx", "SKIP (CONFIG_PPC_FPU is not set)");
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show_result("stfsx", "SKIP (CONFIG_PPC_FPU is not set)");
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}
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static void __init test_lfdx_stfdx(void)
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{
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show_result("lfdx", "SKIP (CONFIG_PPC_FPU is not set)");
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show_result("stfdx", "SKIP (CONFIG_PPC_FPU is not set)");
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}
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#endif /* CONFIG_PPC_FPU */
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#ifdef CONFIG_ALTIVEC
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static void __init test_lvx_stvx(void)
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{
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struct pt_regs regs;
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union {
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vector128 a;
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u32 b[4];
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} c;
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u32 cached_b[4];
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int stepped = -1;
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init_pt_regs(®s);
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/*** lvx ***/
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cached_b[0] = c.b[0] = 923745;
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cached_b[1] = c.b[1] = 2139478;
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cached_b[2] = c.b[2] = 9012;
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cached_b[3] = c.b[3] = 982134;
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regs.gpr[3] = (unsigned long) &c.a;
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regs.gpr[4] = 0;
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/* lvx vrt10, r3, r4 */
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stepped = emulate_step(®s, TEST_LVX(10, 3, 4));
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if (stepped == 1)
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show_result("lvx", "PASS");
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else
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show_result("lvx", "FAIL");
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/*** stvx ***/
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c.b[0] = 4987513;
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c.b[1] = 84313948;
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c.b[2] = 71;
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c.b[3] = 498532;
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/* stvx vrs10, r3, r4 */
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stepped = emulate_step(®s, TEST_STVX(10, 3, 4));
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if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] &&
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cached_b[2] == c.b[2] && cached_b[3] == c.b[3])
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show_result("stvx", "PASS");
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else
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show_result("stvx", "FAIL");
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}
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#else
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static void __init test_lvx_stvx(void)
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{
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show_result("lvx", "SKIP (CONFIG_ALTIVEC is not set)");
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show_result("stvx", "SKIP (CONFIG_ALTIVEC is not set)");
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}
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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static void __init test_lxvd2x_stxvd2x(void)
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{
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struct pt_regs regs;
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union {
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vector128 a;
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u32 b[4];
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} c;
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u32 cached_b[4];
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int stepped = -1;
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init_pt_regs(®s);
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/*** lxvd2x ***/
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cached_b[0] = c.b[0] = 18233;
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cached_b[1] = c.b[1] = 34863571;
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cached_b[2] = c.b[2] = 834;
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cached_b[3] = c.b[3] = 6138911;
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regs.gpr[3] = (unsigned long) &c.a;
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regs.gpr[4] = 0;
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/* lxvd2x vsr39, r3, r4 */
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stepped = emulate_step(®s, TEST_LXVD2X(39, 3, 4));
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if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) {
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show_result("lxvd2x", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("lxvd2x", "PASS (!CPU_FTR_VSX)");
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else
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show_result("lxvd2x", "FAIL");
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}
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/*** stxvd2x ***/
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c.b[0] = 21379463;
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c.b[1] = 87;
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c.b[2] = 374234;
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c.b[3] = 4;
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/* stxvd2x vsr39, r3, r4 */
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stepped = emulate_step(®s, TEST_STXVD2X(39, 3, 4));
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if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] &&
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cached_b[2] == c.b[2] && cached_b[3] == c.b[3] &&
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cpu_has_feature(CPU_FTR_VSX)) {
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show_result("stxvd2x", "PASS");
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} else {
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if (!cpu_has_feature(CPU_FTR_VSX))
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show_result("stxvd2x", "PASS (!CPU_FTR_VSX)");
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else
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show_result("stxvd2x", "FAIL");
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}
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}
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#else
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static void __init test_lxvd2x_stxvd2x(void)
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{
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show_result("lxvd2x", "SKIP (CONFIG_VSX is not set)");
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show_result("stxvd2x", "SKIP (CONFIG_VSX is not set)");
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}
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#endif /* CONFIG_VSX */
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static int __init test_emulate_step(void)
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{
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test_ld();
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test_lwz();
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test_lwzx();
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test_std();
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test_ldarx_stdcx();
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test_lfsx_stfsx();
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test_lfdx_stfdx();
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test_lvx_stvx();
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test_lxvd2x_stxvd2x();
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return 0;
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}
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late_initcall(test_emulate_step);
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