Suzuki K Poulose ff11f5bc5a coresight tmc etr: Detect address width at runtime ... TMC in Coresight SoC-600 advertises the AXI address width in the device configuration register. Bit 16 - AXIAW_VALID 0 - AXI Address Width not valid 1 - Valid AXI Address width in Bits[23-17] Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then 0x20 - 32bit AXI address bus 0x28 - 40bit AXI address bus 0x2c - 44bit AXI address bus 0x30 - 48bit AXI address bus 0x34 - 52bit AXI address bus Use the address bits from the device configuration register, if available. Otherwise, default to 40bit. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-08-28 16:05:49 +02:00
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coresight	coresight tmc etr: Detect address width at runtime	2017-08-28 16:05:49 +02:00
intel_th	hwtracing: intel_th: use dev_groups and not dev_attrs for bus_type	2017-06-09 11:00:46 +02:00
stm	This release has a few updates:	2016-12-15 13:49:34 -08:00