mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 07:34:06 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
99 lines
3.2 KiB
C
99 lines
3.2 KiB
C
/*
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*
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* This file contains the register definitions for the Excalibur
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* Timer TIMER00.
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*
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* Copyright (C) 2001 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __TIMER00_H
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#define __TIMER00_H
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/*
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* Register definitions for the timers
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*/
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#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
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#define TIMER0_CR_B_MSK (0x20)
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#define TIMER0_CR_B_OFST (0x5)
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#define TIMER0_CR_S_MSK (0x10)
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#define TIMER0_CR_S_OFST (0x4)
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#define TIMER0_CR_CI_MSK (0x08)
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#define TIMER0_CR_CI_OFST (0x3)
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#define TIMER0_CR_IE_MSK (0x04)
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#define TIMER0_CR_IE_OFST (0x2)
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#define TIMER0_CR_MODE_MSK (0x3)
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#define TIMER0_CR_MODE_OFST (0)
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#define TIMER0_CR_MODE_FREE (0)
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#define TIMER0_CR_MODE_ONE (1)
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#define TIMER0_CR_MODE_INTVL (2)
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#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
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#define TIMER0_SR_B_MSK (0x20)
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#define TIMER0_SR_B_OFST (0x5)
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#define TIMER0_SR_S_MSK (0x10)
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#define TIMER0_SR_S_OFST (0x4)
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#define TIMER0_SR_CI_MSK (0x08)
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#define TIMER0_SR_CI_OFST (0x3)
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#define TIMER0_SR_IE_MSK (0x04)
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#define TIMER0_SR_IE_OFST (0x2)
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#define TIMER0_SR_MODE_MSK (0x3)
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#define TIMER0_SR_MODE_OFST (0)
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#define TIMER0_SR_MODE_FREE (0)
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#define TIMER0_SR_MODE_ONE (1)
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#define TIMER0_SR_MODE_INTVL (2)
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#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 ))
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#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 ))
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#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 ))
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#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
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#define TIMER1_CR_B_MSK (0x20)
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#define TIMER1_CR_B_OFST (0x5)
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#define TIMER1_CR_S_MSK (0x10)
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#define TIMER1_CR_S_OFST (0x4)
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#define TIMER1_CR_CI_MSK (0x08)
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#define TIMER1_CR_CI_OFST (0x3)
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#define TIMER1_CR_IE_MSK (0x04)
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#define TIMER1_CR_IE_OFST (0x2)
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#define TIMER1_CR_MODE_MSK (0x3)
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#define TIMER1_CR_MODE_OFST (0)
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#define TIMER1_CR_MODE_FREE (0)
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#define TIMER1_CR_MODE_ONE (1)
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#define TIMER1_CR_MODE_INTVL (2)
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#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
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#define TIMER1_SR_B_MSK (0x20)
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#define TIMER1_SR_B_OFST (0x5)
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#define TIMER1_SR_S_MSK (0x10)
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#define TIMER1_SR_S_OFST (0x4)
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#define TIMER1_SR_CI_MSK (0x08)
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#define TIMER1_SR_CI_OFST (0x3)
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#define TIMER1_SR_IE_MSK (0x04)
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#define TIMER1_SR_IE_OFST (0x2)
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#define TIMER1_SR_MODE_MSK (0x3)
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#define TIMER1_SR_MODE_OFST (0)
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#define TIMER1_SR_MODE_FREE (0)
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#define TIMER1_SR_MODE_ONE (1)
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#define TIMER1_SR_MODE_INTVL (2)
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#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 ))
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#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 ))
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#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 ))
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#endif /* __TIMER00_H */
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