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Depending on the sensor configuration it might be required to adjust the CSIS's output pixel clock so it is greater than its input pixel clock, in order to avoid the input data FIFO overflow. Use platform data to select SCLK_CSIS clock from CMU as a source, rather than CSI APB clock. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
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* Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
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*
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* Samsung S5P/Exynos SoC series MIPI CSIS device support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_
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#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__
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/**
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* struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
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* @clk_rate: bus clock frequency
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* @wclk_source: CSI wrapper clock selection: 0 - bus clock, 1 - ext. SCLK_CAM
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* @lanes: number of data lanes used
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* @hs_settle: HS-RX settle time
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*/
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struct s5p_platform_mipi_csis {
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unsigned long clk_rate;
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u8 wclk_source;
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u8 lanes;
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u8 hs_settle;
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};
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/**
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* s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
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* @id: MIPI-CSIS harware instance index (0...1)
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* @on: true to enable D-PHY and deassert its reset
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* false to disable D-PHY
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* @return: 0 on success, or negative error code on failure
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*/
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int s5p_csis_phy_enable(int id, bool on);
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#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */
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