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ModPhy Common lanes can provide the clock gating status for the important system PLLs such as Gen2 USB3PCIE2 PLL, DMIPCIE3 PLL, SATA PLL and MIPI PLL. On SPT, in addition to the crystal oscillator clock, the 100Mhz Gen2 USB3PCI2 PLL clock is used as the PLL reference clock and Gen2 PLL idling is a necessary condition for the platform to go into low power states like PC10 and S0ix. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
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