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368dd5acd1
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/* MN10300 System definitions
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <asm/cpu-regs.h>
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#include <asm/intctl-regs.h>
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <linux/kernel.h>
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#include <linux/irqflags.h>
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#include <asm/atomic.h>
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#if !defined(CONFIG_LAZY_SAVE_FPU)
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struct fpu_state_struct;
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extern asmlinkage void fpu_save(struct fpu_state_struct *);
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#define switch_fpu(prev, next) \
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do { \
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if ((prev)->thread.fpu_flags & THREAD_HAS_FPU) { \
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(prev)->thread.fpu_flags &= ~THREAD_HAS_FPU; \
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(prev)->thread.uregs->epsw &= ~EPSW_FE; \
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fpu_save(&(prev)->thread.fpu_state); \
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} \
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} while (0)
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#else
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#define switch_fpu(prev, next) do {} while (0)
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#endif
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struct task_struct;
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struct thread_struct;
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extern asmlinkage
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struct task_struct *__switch_to(struct thread_struct *prev,
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struct thread_struct *next,
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struct task_struct *prev_task);
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/* context switching is now performed out-of-line in switch_to.S */
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#define switch_to(prev, next, last) \
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do { \
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switch_fpu(prev, next); \
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current->thread.wchan = (u_long) __builtin_return_address(0); \
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(last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
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mb(); \
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current->thread.wchan = 0; \
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} while (0)
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#define arch_align_stack(x) (x)
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#define nop() asm volatile ("nop")
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* For now, "wmb()" doesn't actually do anything, as all
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* Intel CPU's follow what Intel calls a *Processor Order*,
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* in which all writes are seen in the program order even
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* outside the CPU.
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*
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* I expect future Intel CPU's to have a weaker ordering,
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* but I'd also expect them to finally get their act together
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* and add some real memory barriers if so.
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*
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* Some non intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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#define mb() asm volatile ("": : :"memory")
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#define rmb() mb()
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#define wmb() asm volatile ("": : :"memory")
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#else /* CONFIG_SMP */
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#endif /* CONFIG_SMP */
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define read_barrier_depends() do {} while (0)
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#define smp_read_barrier_depends() do {} while (0)
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_SYSTEM_H */
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