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b095ae2b9f
There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
12 lines
240 B
ArmAsm
12 lines
240 B
ArmAsm
#include <linux/linkage.h>
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#include <linux/init.h>
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#include "sleep.h"
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.section ".text.head", "ax"
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ENTRY(tegra_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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