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0c02a20ff7
Just make it depend on BROKEN for now, in case people scream really loud about it (and because we might want to keep some of this logic for an upcoming BIOS workaround, so I don't just want to rip it out entirely just yet). But for graphics devices, it really ought to be unnecessary. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
112 lines
3.8 KiB
Plaintext
112 lines
3.8 KiB
Plaintext
Linux IOMMU Support
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===================
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The architecture spec can be obtained from the below location.
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http://www.intel.com/technology/virtualization/
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This guide gives a quick cheat sheet for some basic understanding.
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Some Keywords
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DMAR - DMA remapping
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DRHD - DMA Engine Reporting Structure
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RMRR - Reserved memory Region Reporting Structure
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ZLR - Zero length reads from PCI devices
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IOVA - IO Virtual address.
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Basic stuff
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-----------
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ACPI enumerates and lists the different DMA engines in the platform, and
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device scope relationships between PCI devices and which DMA engine controls
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them.
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What is RMRR?
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-------------
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There are some devices the BIOS controls, for e.g USB devices to perform
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PS2 emulation. The regions of memory used for these devices are marked
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reserved in the e820 map. When we turn on DMA translation, DMA to those
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regions will fail. Hence BIOS uses RMRR to specify these regions along with
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devices that need to access these regions. OS is expected to setup
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unity mappings for these regions for these devices to access these regions.
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How is IOVA generated?
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---------------------
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Well behaved drivers call pci_map_*() calls before sending command to device
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that needs to perform DMA. Once DMA is completed and mapping is no longer
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required, device performs a pci_unmap_*() calls to unmap the region.
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The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
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device has its own domain (hence protection). Devices under p2p bridges
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share the virtual address with all devices under the p2p bridge due to
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transaction id aliasing for p2p bridges.
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IOVA generation is pretty generic. We used the same technique as vmalloc()
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but these are not global address spaces, but separate for each domain.
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Different DMA engines may support different number of domains.
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We also allocate guard pages with each mapping, so we can attempt to catch
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any overflow that might happen.
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Graphics Problems?
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------------------
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If you encounter issues with graphics devices, you can try adding
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option intel_iommu=igfx_off to turn off the integrated graphics engine.
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If this fixes anything, please ensure you file a bug reporting the problem.
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Some exceptions to IOVA
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-----------------------
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Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
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The same is true for peer to peer transactions. Hence we reserve the
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address from PCI MMIO ranges so they are not allocated for IOVA addresses.
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Fault reporting
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---------------
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When errors are reported, the DMA engine signals via an interrupt. The fault
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reason and device that caused it with fault reason is printed on console.
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See below for sample.
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Boot Message Sample
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-------------------
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Something like this gets printed indicating presence of DMAR tables
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in ACPI.
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ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
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When DMAR is being processed and initialized by ACPI, prints DMAR locations
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and any RMRR's processed.
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ACPI DMAR:Host address width 36
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ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
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ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
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ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
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ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
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ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
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When DMAR is enabled for use, you will notice..
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PCI-DMA: Using DMAR IOMMU
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Fault reporting
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---------------
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DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
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DMAR:[fault reason 05] PTE Write access is not set
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DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
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DMAR:[fault reason 05] PTE Write access is not set
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TBD
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----
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- For compatibility testing, could use unity map domain for all devices, just
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provide a 1-1 for all useful memory under a single domain for all devices.
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- API for paravirt ops for abstracting functionality for VMM folks.
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