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https://github.com/edk2-porting/linux-next.git
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6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
112 lines
2.3 KiB
ArmAsm
112 lines
2.3 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* A couple of functions stolen from arch/ppc/kernel/misc.S for UML
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* by Chris Emerson.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/processor.h>
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#include "ppc_asm.h"
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#if defined(CONFIG_4xx) || defined(CONFIG_8xx)
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#define CACHE_LINE_SIZE 16
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#define LG_CACHE_LINE_SIZE 4
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#define MAX_COPY_PREFETCH 1
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#else
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#define CACHE_LINE_SIZE 32
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#define LG_CACHE_LINE_SIZE 5
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#define MAX_COPY_PREFETCH 4
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#endif /* CONFIG_4xx || CONFIG_8xx */
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.text
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/*
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* Clear a page using the dcbz instruction, which doesn't cause any
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* memory traffic (except to write out any cache lines which get
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* displaced). This only works on cacheable memory.
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*/
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_GLOBAL(clear_page)
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li r0,4096/CACHE_LINE_SIZE
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mtctr r0
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#ifdef CONFIG_8xx
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li r4, 0
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1: stw r4, 0(r3)
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stw r4, 4(r3)
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stw r4, 8(r3)
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stw r4, 12(r3)
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#else
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1: dcbz 0,r3
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#endif
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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blr
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/*
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* Copy a whole page. We use the dcbz instruction on the destination
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* to reduce memory traffic (it eliminates the unnecessary reads of
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* the destination into cache). This requires that the destination
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* is cacheable.
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*/
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#define COPY_16_BYTES \
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lwz r6,4(r4); \
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lwz r7,8(r4); \
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lwz r8,12(r4); \
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lwzu r9,16(r4); \
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stw r6,4(r3); \
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stw r7,8(r3); \
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stw r8,12(r3); \
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stwu r9,16(r3)
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_GLOBAL(copy_page)
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addi r3,r3,-4
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addi r4,r4,-4
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li r5,4
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#ifndef CONFIG_8xx
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#if MAX_COPY_PREFETCH > 1
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li r0,MAX_COPY_PREFETCH
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li r11,4
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mtctr r0
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11: dcbt r11,r4
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addi r11,r11,CACHE_LINE_SIZE
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bdnz 11b
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#else /* MAX_COPY_PREFETCH == 1 */
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dcbt r5,r4
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li r11,CACHE_LINE_SIZE+4
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#endif /* MAX_COPY_PREFETCH */
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#endif /* CONFIG_8xx */
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li r0,4096/CACHE_LINE_SIZE
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mtctr r0
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1:
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#ifndef CONFIG_8xx
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dcbt r11,r4
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dcbz r5,r3
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#endif
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COPY_16_BYTES
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#if CACHE_LINE_SIZE >= 32
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COPY_16_BYTES
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#if CACHE_LINE_SIZE >= 64
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COPY_16_BYTES
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COPY_16_BYTES
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#if CACHE_LINE_SIZE >= 128
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COPY_16_BYTES
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COPY_16_BYTES
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COPY_16_BYTES
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COPY_16_BYTES
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#endif
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#endif
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#endif
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bdnz 1b
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blr
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