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https://github.com/edk2-porting/linux-next.git
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fcbd458e95
This patch adds support for db8500 chip version 2. The TCDM memory address of the PRCMU is changed and dynamic detection of that is added. Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
172 lines
4.4 KiB
C
172 lines
4.4 KiB
C
/*
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* Copyright (C) 2008-2009 ST-Ericsson
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*
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* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/devices.h>
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#include "devices-db8500.h"
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static struct platform_device *platform_devs[] __initdata = {
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&u8500_gpio_devs[0],
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&u8500_gpio_devs[1],
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&u8500_gpio_devs[2],
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&u8500_gpio_devs[3],
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&u8500_gpio_devs[4],
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&u8500_gpio_devs[5],
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&u8500_gpio_devs[6],
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&u8500_gpio_devs[7],
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&u8500_gpio_devs[8],
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&u8500_dma40_device,
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};
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/* minimum static i/o mapping required to boot U8500 platforms */
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static struct map_desc u8500_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
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__MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
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};
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static struct map_desc u8500_ed_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
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};
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static struct map_desc u8500_v1_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
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};
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static struct map_desc u8500_v2_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
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};
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/*
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* Functions to differentiate between later ASICs
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* We look into the end of the ROM to locate the hardcoded ASIC ID.
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* This is only needed to differentiate between minor revisions and
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* process variants of an ASIC, the major revisions are encoded in
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* the cpuid.
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*/
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#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4)
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#define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4)
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#define U8500_ASIC_REV_ED 0x01
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#define U8500_ASIC_REV_V10 0xA0
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#define U8500_ASIC_REV_V11 0xA1
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#define U8500_ASIC_REV_V20 0xB0
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/**
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* struct db8500_asic_id - fields of the ASIC ID
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* @process: the manufacturing process, 0x40 is 40 nm
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* 0x00 is "standard"
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* @partnumber: hithereto 0x8500 for DB8500
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* @revision: version code in the series
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* This field definion is not formally defined but makes
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* sense.
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*/
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struct db8500_asic_id {
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u8 process;
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u16 partnumber;
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u8 revision;
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};
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/* This isn't going to change at runtime */
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static struct db8500_asic_id db8500_id;
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static void __init get_db8500_asic_id(void)
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{
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u32 asicid;
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if (cpu_is_u8500v1() || cpu_is_u8500ed())
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asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1));
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else if (cpu_is_u8500v2())
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asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2));
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else
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BUG();
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db8500_id.process = (asicid >> 24);
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db8500_id.partnumber = (asicid >> 16) & 0xFFFFU;
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db8500_id.revision = asicid & 0xFFU;
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}
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bool cpu_is_u8500v10(void)
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{
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return (db8500_id.revision == U8500_ASIC_REV_V10);
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}
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bool cpu_is_u8500v11(void)
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{
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return (db8500_id.revision == U8500_ASIC_REV_V11);
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}
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bool cpu_is_u8500v20(void)
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{
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return (db8500_id.revision == U8500_ASIC_REV_V20);
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}
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void __init u8500_map_io(void)
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{
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ux500_map_io();
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iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
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if (cpu_is_u8500ed())
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iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
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else if (cpu_is_u8500v1())
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iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
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else if (cpu_is_u8500v2())
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iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
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/* Read out the ASIC ID as early as we can */
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get_db8500_asic_id();
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}
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/*
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* This function is called from the board init
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*/
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void __init u8500_init_devices(void)
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{
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/* Display some ASIC boilerplate */
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pr_info("DB8500: process: %02x, revision ID: 0x%02x\n",
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db8500_id.process, db8500_id.revision);
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if (cpu_is_u8500ed())
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pr_info("DB8500: Early Drop (ED)\n");
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else if (cpu_is_u8500v10())
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pr_info("DB8500: version 1.0\n");
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else if (cpu_is_u8500v11())
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pr_info("DB8500: version 1.1\n");
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else if (cpu_is_u8500v20())
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pr_info("DB8500: version 2.0\n");
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else
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pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
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if (cpu_is_u8500ed())
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dma40_u8500ed_fixup();
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db8500_add_rtc();
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platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
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return ;
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}
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