mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-11-19 08:05:27 +08:00
559fb51ba7
- Use extern prefix for functions required.
- Removed a lot of wrappers, including t1_read/write_reg_4.
- Removed various macros, using native kernel calls now.
- Enumerated various #defines.
- Removed a lot of shared code which is not currently used in "NIC only" mode.
- Removed dead code.
Documentation/networking/cxgb.txt:
- Updated release notes for version 2.1.1
drivers/net/chelsio/ch_ethtool.h
- removed file, no longer using ETHTOOL namespace.
drivers/net/chelsio/common.h
- moved code from osdep.h to common.h
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/cphy.h
- removed dead code.
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/cxgb2.c
- use DMA_{32,64}BIT_MASK in include/linux/dma-mapping.h.
- removed unused code.
- use printk message for link info resembling drivers/net/mii.c.
- no longer using the MODULE_xxx namespace.
- no longer using "pci_" namespace.
- no longer using ETHTOOL namespace.
drivers/net/chelsio/cxgb2.h
- removed file, merged into common.h
drivers/net/chelsio/elmer0.h
- removed dead code.
- added various enums.
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/espi.c
- removed various macros, using native kernel calls now.
- removed a lot of wrappers, including t1_read/write_reg_4.
drivers/net/chelsio/espi.h
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/gmac.h
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/mv88x201x.c
- changes to sync with Chelsio TOT.
drivers/net/chelsio/osdep.h
- removed file, consolidation. osdep was used to translate wrapper functions
since our code supports multiple OSs. removed wrappers.
drivers/net/chelsio/pm3393.c
- removed various macros, using native kernel calls now.
- removed a lot of wrappers, including t1_read/write_reg_4.
- removed unused code.
drivers/net/chelsio/regs.h
- added a few register entries for future and current feature support.
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/sge.c
- rewrote large portion of scatter-gather engine to stabilize
performance.
- using u8/u16/u32 kernel types instead of __u8/__u16/__u32 compiler
types.
drivers/net/chelsio/sge.h
- rewrote large portion of scatter-gather engine to stabilize
performance.
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/subr.c
- merged tp.c into subr.c
- removed various macros, using native kernel calls now.
- removed a lot of wrappers, including t1_read/write_reg_4.
- removed unused code.
drivers/net/chelsio/suni1x10gexp_regs.h
- modified copyright and authorship of file.
- added comment to #endif indicating which symbol it closes.
drivers/net/chelsio/tp.c
- removed file, merged into subr.c.
drivers/net/chelsio/tp.h
- removed file.
include/linux/pci_ids.h
- patched to include PCI_VENDOR_ID_CHELSIO 0x1425, removed define from
our code.
214 lines
13 KiB
C
214 lines
13 KiB
C
/*****************************************************************************
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* *
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* File: suni1x10gexp_regs.h *
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* $Revision: 1.9 $ *
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* $Date: 2005/06/22 00:17:04 $ *
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* Description: *
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* PMC/SIERRA (pm3393) MAC-PHY functionality. *
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* part of the Chelsio 10Gb Ethernet Driver. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License, version 2, as *
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* published by the Free Software Foundation. *
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* *
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* You should have received a copy of the GNU General Public License along *
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* with this program; if not, write to the Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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* *
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* http://www.chelsio.com *
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* *
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* Maintainers: maintainers@chelsio.com *
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* *
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* Authors: PMC/SIERRA *
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* *
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* History: *
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* *
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****************************************************************************/
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#ifndef _CXGB_SUNI1x10GEXP_REGS_H_
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#define _CXGB_SUNI1x10GEXP_REGS_H_
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/******************************************************************************/
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/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
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/******************************************************************************/
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/* Refer to the Register Bit Masks bellow for the naming of each register and */
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/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
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/******************************************************************************/
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#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
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#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
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#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
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#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
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#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
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#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
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#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
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#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
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#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
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#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
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#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
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#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
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#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
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#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
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#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
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#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
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#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
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#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
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#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
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#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
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#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
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#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
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#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
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#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
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#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
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#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
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#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
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#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104
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#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105
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#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
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#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
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#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
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#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
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#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
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#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
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#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
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#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
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#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
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#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
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#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
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#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
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#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
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#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
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#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045
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#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047
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#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048
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#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049
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#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084
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#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085
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#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6
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#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7
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#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C
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#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D
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#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282
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#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283
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/******************************************************************************/
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/* -- End register offset definitions -- */
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/******************************************************************************/
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/******************************************************************************/
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/** SUNI-1x10GE-XP REGISTER BIT MASKS **/
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/******************************************************************************/
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/*----------------------------------------------------------------------------
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* Register 0x0004: S/UNI-1x10GE-XP Device Status
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* Bit 9 TOP_SXRA_EXPIRED
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* Bit 8 TOP_MDIO_BUSY
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* Bit 7 TOP_DTRB
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* Bit 6 TOP_EXPIRED
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* Bit 5 TOP_PAUSED
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* Bit 4 TOP_PL4_ID_DOOL
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* Bit 3 TOP_PL4_IS_DOOL
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* Bit 2 TOP_PL4_ID_ROOL
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* Bit 1 TOP_PL4_IS_ROOL
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* Bit 0 TOP_PL4_OUT_ROOL
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*----------------------------------------------------------------------------*/
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#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200
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#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040
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#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010
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#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008
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#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004
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#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002
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#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001
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/*----------------------------------------------------------------------------
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* Register 0x000E:PM3393 Global interrupt enable
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* Bit 15 TOP_INTE
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*----------------------------------------------------------------------------*/
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#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000
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/*----------------------------------------------------------------------------
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* Register 0x2040: RXXG Configuration 1
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* Bit 15 RXXG_RXEN
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* Bit 14 RXXG_ROCF
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* Bit 13 RXXG_PAD_STRIP
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* Bit 10 RXXG_PUREP
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* Bit 9 RXXG_LONGP
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* Bit 8 RXXG_PARF
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* Bit 7 RXXG_FLCHK
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* Bit 5 RXXG_PASS_CTRL
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* Bit 3 RXXG_CRC_STRIP
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* Bit 2-0 RXXG_MIFG
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*----------------------------------------------------------------------------*/
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#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000
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#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400
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#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080
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#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008
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/*----------------------------------------------------------------------------
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* Register 0x2070: RXXG Address Filter Control 2
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* Bit 1 RXXG_PMODE
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* Bit 0 RXXG_MHASH_EN
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*----------------------------------------------------------------------------*/
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#define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002
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#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001
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/*----------------------------------------------------------------------------
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* Register 0x2100: MSTAT Control
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* Bit 2 MSTAT_WRITE
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* Bit 1 MSTAT_CLEAR
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* Bit 0 MSTAT_SNAP
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*----------------------------------------------------------------------------*/
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#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002
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#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001
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/*----------------------------------------------------------------------------
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* Register 0x3040: TXXG Configuration Register 1
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* Bit 15 TXXG_TXEN0
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* Bit 13 TXXG_HOSTPAUSE
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* Bit 12-7 TXXG_IPGT
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* Bit 5 TXXG_32BIT_ALIGN
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* Bit 4 TXXG_CRCEN
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* Bit 3 TXXG_FCTX
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* Bit 2 TXXG_FCRX
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* Bit 1 TXXG_PADEN
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* Bit 0 TXXG_SPRE
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*----------------------------------------------------------------------------*/
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#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000
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#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7
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#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020
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#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010
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#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008
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#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004
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#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002
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#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
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