mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 23:53:55 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
355 lines
11 KiB
C
355 lines
11 KiB
C
/*
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* linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
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*
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* Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr>
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*
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* Created 28 Aug 2001 by Ghozlane Toumi
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*/
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#ifndef _SSTFB_H_
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#define _SSTFB_H_
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/*
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*
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* Debug Stuff
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*
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*/
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#ifdef SST_DEBUG
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# define dprintk(X...) printk("sstfb: " X)
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# define SST_DEBUG_REG 1
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# define SST_DEBUG_FUNC 1
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# define SST_DEBUG_VAR 1
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#else
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# define dprintk(X...)
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# define SST_DEBUG_REG 0
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# define SST_DEBUG_FUNC 0
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# define SST_DEBUG_VAR 0
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#endif
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#if (SST_DEBUG_REG > 0)
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# define r_dprintk(X...) dprintk(X)
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#else
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# define r_dprintk(X...)
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#endif
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#if (SST_DEBUG_REG > 1)
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# define r_ddprintk(X...) dprintk(" " X)
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#else
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# define r_ddprintk(X...)
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#endif
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#if (SST_DEBUG_FUNC > 0)
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# define f_dprintk(X...) dprintk(X)
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#else
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# define f_dprintk(X...)
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#endif
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#if (SST_DEBUG_FUNC > 1)
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# define f_ddprintk(X...) dprintk(" " X)
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#else
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# define f_ddprintk(X...)
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#endif
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#if (SST_DEBUG_FUNC > 2)
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# define f_dddprintk(X...) dprintk(" " X)
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#else
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# define f_dddprintk(X...)
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#endif
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#if (SST_DEBUG_VAR > 0)
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# define v_dprintk(X...) dprintk(X)
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# define print_var(V, X...) \
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{ \
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dprintk(X); \
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printk(" :\n"); \
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sst_dbg_print_var(V); \
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}
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#else
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# define v_dprintk(X...)
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# define print_var(X,Y...)
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#endif
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#define eprintk(X...) printk(KERN_ERR "sstfb: " X)
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#define iprintk(X...) printk(KERN_INFO "sstfb: " X)
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#define wprintk(X...) printk(KERN_WARNING "sstfb: " X)
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#define BIT(x) (1ul<<(x))
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#define POW2(x) (1ul<<(x))
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/*
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*
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* Const
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*
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*/
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/* pci stuff */
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#define PCI_INIT_ENABLE 0x40
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# define PCI_EN_INIT_WR BIT(0)
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# define PCI_EN_FIFO_WR BIT(1)
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# define PCI_REMAP_DAC BIT(2)
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#define PCI_VCLK_ENABLE 0xc0 /* enable video */
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#define PCI_VCLK_DISABLE 0xe0
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/* register offsets from memBaseAddr */
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#define STATUS 0x0000
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# define STATUS_FBI_BUSY BIT(7)
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#define FBZMODE 0x0110
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# define EN_CLIPPING BIT(0) /* enable clipping */
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# define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
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# define EN_ALPHA_WRITE BIT(10)
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# define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
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#define LFBMODE 0x0114
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# define LFB_565 0 /* bits 3:0 .16 bits RGB */
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# define LFB_888 4 /* 24 bits RGB */
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# define LFB_8888 5 /* 32 bits ARGB */
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# define WR_BUFF_FRONT 0 /* write buf select (front) */
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# define WR_BUFF_BACK (1 << 4) /* back */
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# define RD_BUFF_FRONT 0 /* read buff select (front) */
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# define RD_BUFF_BACK (1 << 6) /* back */
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# define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
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# define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
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# define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
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# define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */
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# define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
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# define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
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#define CLIP_LEFT_RIGHT 0x0118
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#define CLIP_LOWY_HIGHY 0x011c
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#define NOPCMD 0x0120
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#define FASTFILLCMD 0x0124
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#define SWAPBUFFCMD 0x0128
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#define FBIINIT4 0x0200 /* misc controls */
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# define FAST_PCI_READS 0 /* 1 waitstate */
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# define SLOW_PCI_READS BIT(0) /* 2 ws */
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# define LFB_READ_AHEAD BIT(1)
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#define BACKPORCH 0x0208
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#define VIDEODIMENSIONS 0x020c
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#define FBIINIT0 0x0210 /* misc+fifo controls */
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# define EN_VGA_PASSTHROUGH BIT(0)
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# define FBI_RESET BIT(1)
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# define FIFO_RESET BIT(2)
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#define FBIINIT1 0x0214 /* PCI + video controls */
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# define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/
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# define FAST_PCI_WRITES 0 /* 0 ws */
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# define SLOW_PCI_WRITES BIT(1) /* 1 ws */
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# define EN_LFB_READ BIT(3)
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# define TILES_IN_X_SHIFT 4
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# define VIDEO_RESET BIT(8)
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# define EN_BLANKING BIT(12)
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# define EN_DATA_OE BIT(13)
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# define EN_BLANK_OE BIT(14)
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# define EN_HVSYNC_OE BIT(15)
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# define EN_DCLK_OE BIT(16)
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# define SEL_INPUT_VCLK_2X 0 /* bit 17 */
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# define SEL_INPUT_VCLK_SLAVE BIT(17)
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# define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */
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# define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20)
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# define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20)
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# define EN_24BPP BIT(22)
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# define TILES_IN_X_MSB_SHIFT 24 /* v2 */
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# define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */
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# define VCLK_DEL_SHIFT 29 /* vclk in delay */
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#define FBIINIT2 0x0218 /* Dram controls */
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# define EN_FAST_RAS_READ BIT(5)
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# define EN_DRAM_OE BIT(6)
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# define EN_FAST_RD_AHEAD_WR BIT(7)
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# define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */
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# define SWAP_DACVSYNC 0
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# define SWAP_DACDATA0 (1 << 9)
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# define SWAP_FIFO_STALL (2 << 9)
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# define EN_RD_AHEAD_FIFO BIT(21)
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# define EN_DRAM_REFRESH BIT(22)
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# define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */
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#define DAC_READ FBIINIT2 /* in remap mode */
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#define FBIINIT3 0x021c /* fbi controls */
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# define DISABLE_TEXTURE BIT(6)
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# define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap substraction value */
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#define HSYNC 0x0220
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#define VSYNC 0x0224
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#define DAC_DATA 0x022c
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# define DAC_READ_CMD BIT(11) /* set read dacreg mode */
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#define FBIINIT5 0x0244 /* v2 specific */
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# define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/
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# define HDOUBLESCAN BIT(20)
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# define VDOUBLESCAN BIT(21)
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# define HSYNC_HIGH BIT(23)
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# define VSYNC_HIGH BIT(24)
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# define INTERLACE BIT(26)
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#define FBIINIT6 0x0248 /* v2 specific */
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# define TILES_IN_X_LSB_SHIFT 30 /* v2 */
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#define FBIINIT7 0x024c /* v2 specific */
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#define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
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#define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */
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#define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
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#define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
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#define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */
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#define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */
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#define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */
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#define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
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#define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */
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#define BLTSIZE 0x02e8 /* BitBLT width and height */
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#define BLTROP 0x02ec /* BitBLT Raster operations */
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# define BLTROP_COPY 0x0cccc
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# define BLTROP_INVERT 0x05555
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# define BLTROP_XOR 0x06666
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#define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */
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#define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */
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# define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
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# define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
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# define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */
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# define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
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#define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
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# define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */
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/* Dac Registers */
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#define DACREG_WMA 0x0 /* pixel write mode address */
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#define DACREG_LUT 0x01 /* color value */
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#define DACREG_RMR 0x02 /* pixel mask */
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#define DACREG_RMA 0x03 /* pixel read mode address */
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/*Dac registers in indexed mode (TI, ATT dacs) */
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#define DACREG_ADDR_I DACREG_WMA
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#define DACREG_DATA_I DACREG_RMR
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#define DACREG_RMR_I 0x00
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#define DACREG_CR0_I 0x01
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# define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */
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# define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */
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# define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */
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# define DACREG_CR0_16BPP 0x30 /* mode 3 */
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# define DACREG_CR0_24BPP 0x50 /* mode 5 */
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#define DACREG_CR1_I 0x05
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#define DACREG_CC_I 0x06
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# define DACREG_CC_CLKA BIT(7) /* clk A controled by regs */
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# define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */
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# define DACREG_CC_CLKB BIT(3) /* clk B controled by regs */
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# define DACREG_CC_CLKB_D 3 /* clkB uses reg D */
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#define DACREG_AC0_I 0x48 /* clock A reg C */
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#define DACREG_AC1_I 0x49
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#define DACREG_BD0_I 0x6c /* clock B reg D */
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#define DACREG_BD1_I 0x6d
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/* identification constants */
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#define DACREG_MIR_TI 0x97
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#define DACREG_DIR_TI 0x09
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#define DACREG_MIR_ATT 0x84
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#define DACREG_DIR_ATT 0x09
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/* ics dac specific registers */
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#define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */
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#define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */
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#define DACREG_ICS_CMD 0x06 /* command */
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# define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
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# define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
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# define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */
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#define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */
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/*
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* pll parameter register:
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* indexed : write addr to PLLWMA, write data in PLLDATA.
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* for reads use PLLRMA .
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* 8 freq registers (0-7) for video clock (CLK0)
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* 2 freq registers (a-b) for graphic clock (CLK1)
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*/
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#define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
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#define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */
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#define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */
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#define DACREG_ICS_PLL_CTRL 0x0e
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# define DACREG_ICS_CLK0 BIT(5)
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# define DACREG_ICS_CLK0_0 0
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# define DACREG_ICS_CLK1_A 0 /* bit4 */
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/* sst default init registers */
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#define FBIINIT0_DEFAULT EN_VGA_PASSTHROUGH
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#define FBIINIT1_DEFAULT \
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( \
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FAST_PCI_WRITES \
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/* SLOW_PCI_WRITES*/ \
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| VIDEO_RESET \
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| 10 << TILES_IN_X_SHIFT\
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| SEL_SOURCE_VCLK_2X_SEL\
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| EN_LFB_READ \
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)
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#define FBIINIT2_DEFAULT \
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( \
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SWAP_DACVSYNC \
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| EN_DRAM_OE \
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| DRAM_REFRESH_16 \
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| EN_DRAM_REFRESH \
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| EN_FAST_RAS_READ \
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| EN_RD_AHEAD_FIFO \
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| EN_FAST_RD_AHEAD_WR \
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)
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#define FBIINIT3_DEFAULT \
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( DISABLE_TEXTURE )
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#define FBIINIT4_DEFAULT \
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( \
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FAST_PCI_READS \
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/* SLOW_PCI_READS*/ \
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| LFB_READ_AHEAD \
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)
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/* Careful with this one : writing back the data just read will trash the DAC
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reading some fields give logic value on pins, but setting this field will
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set the source signal driving the pin. conclusion : just use the default
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as a base before writing back .
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*/
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#define FBIINIT6_DEFAULT (0x0)
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/*
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*
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* Misc Const
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*
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*/
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/* used to know witch clock to set */
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enum {
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VID_CLOCK=0,
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GFX_CLOCK=1,
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};
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/* freq max */
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#define DAC_FREF 14318 /* DAC reference freq (Khz) */
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#define VCO_MAX 260000
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/*
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* driver structs
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*/
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struct pll_timing {
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unsigned int m;
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unsigned int n;
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unsigned int p;
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};
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struct dac_switch {
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char * name;
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int (*detect) (struct fb_info *info);
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int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock);
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void (*set_vidmod) (struct fb_info *info, const int bpp);
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};
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struct sst_spec {
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char * name;
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int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */
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int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */
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};
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struct sstfb_par {
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unsigned int yDim;
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unsigned int hSyncOn; /* hsync_len */
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unsigned int hSyncOff; /* left_margin + xres + right_margin */
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unsigned int hBackPorch;/* left_margin */
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unsigned int vSyncOn;
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unsigned int vSyncOff;
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unsigned int vBackPorch;
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struct pll_timing pll;
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unsigned int tiles_in_X;/* num of tiles in X res */
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u8 __iomem *mmio_vbase;
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struct dac_switch dac_sw; /* dac specific functions */
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struct pci_dev *dev;
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int type;
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u8 revision;
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int gfx_clock; /* status */
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};
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#endif /* _SSTFB_H_ */
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