mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 15:43:59 +08:00
fa142ff5b3
The watchdog infrastructure in Dove is no different from that in Orion5x or Kirkwood, so let's enable it for Dove. The only things missing are a few register settings in Dove's bridge-regs.h. Rather than duplicating the same register bit masks for the RSTOUTn_MASK and BRIDGE_CAUSE registers, move the definitions into the watchdog driver itself. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
37 lines
1011 B
C
37 lines
1011 B
C
/*
|
|
* arch/arm/mach-orion5x/include/mach/bridge-regs.h
|
|
*
|
|
* Orion CPU Bridge Registers
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_BRIDGE_REGS_H
|
|
#define __ASM_ARCH_BRIDGE_REGS_H
|
|
|
|
#include <mach/orion5x.h>
|
|
|
|
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
|
|
|
|
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
|
|
|
|
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
|
|
|
|
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
|
|
|
|
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
|
|
|
|
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
|
|
|
|
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
|
|
|
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
|
|
|
|
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
|
|
|
|
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
|
|
#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
|
|
#endif
|