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9f5dc91b69
Update the power domain power states for final production chip capability. OFF mode, OSWR etc have been descoped for various domains. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
331 lines
9.1 KiB
C
331 lines
9.1 KiB
C
/*
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* OMAP54XX Power domains framework
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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* Paul Walmsley (paul@pwsan.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include "powerdomain.h"
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#include "prcm-common.h"
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#include "prcm44xx.h"
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#include "prm54xx.h"
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#include "prcm_mpu54xx.h"
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/* core_54xx_pwrdm: CORE power domain */
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static struct powerdomain core_54xx_pwrdm = {
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.name = "core_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_CORE_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 5,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* core_nret_bank */
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[1] = PWRSTS_OFF_RET, /* core_ocmram */
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[2] = PWRSTS_OFF_RET, /* core_other_bank */
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[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
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[4] = PWRSTS_OFF_RET, /* ipu_unicache */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* core_nret_bank */
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[1] = PWRSTS_OFF_RET, /* core_ocmram */
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[2] = PWRSTS_OFF_RET, /* core_other_bank */
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[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
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[4] = PWRSTS_OFF_RET, /* ipu_unicache */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* abe_54xx_pwrdm: Audio back end power domain */
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static struct powerdomain abe_54xx_pwrdm = {
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.name = "abe_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_ABE_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* aessmem */
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[1] = PWRSTS_OFF_RET, /* periphmem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* aessmem */
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[1] = PWRSTS_OFF_RET, /* periphmem */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
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static struct powerdomain coreaon_54xx_pwrdm = {
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.name = "coreaon_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_COREAON_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_ON,
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};
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/* dss_54xx_pwrdm: Display subsystem power domain */
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static struct powerdomain dss_54xx_pwrdm = {
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.name = "dss_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_DSS_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* dss_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* dss_mem */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
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static struct powerdomain cpu0_54xx_pwrdm = {
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.name = "cpu0_pwrdm",
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.voltdm = { .name = "mpu" },
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.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
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.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* cpu0_l1 */
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},
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};
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/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
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static struct powerdomain cpu1_54xx_pwrdm = {
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.name = "cpu1_pwrdm",
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.voltdm = { .name = "mpu" },
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.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
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.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* cpu1_l1 */
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},
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};
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/* emu_54xx_pwrdm: Emulation power domain */
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static struct powerdomain emu_54xx_pwrdm = {
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.name = "emu_pwrdm",
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.voltdm = { .name = "wkup" },
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.prcm_offs = OMAP54XX_PRM_EMU_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* emu_bank */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* emu_bank */
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},
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};
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/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
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static struct powerdomain mpu_54xx_pwrdm = {
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.name = "mpu_pwrdm",
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.voltdm = { .name = "mpu" },
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.prcm_offs = OMAP54XX_PRM_MPU_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_RET,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* mpu_l2 */
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[1] = PWRSTS_RET, /* mpu_ram */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* mpu_l2 */
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[1] = PWRSTS_OFF_RET, /* mpu_ram */
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},
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};
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/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
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static struct powerdomain custefuse_54xx_pwrdm = {
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.name = "custefuse_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_ON,
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* dsp_54xx_pwrdm: Tesla processor power domain */
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static struct powerdomain dsp_54xx_pwrdm = {
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.name = "dsp_pwrdm",
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.voltdm = { .name = "mm" },
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.prcm_offs = OMAP54XX_PRM_DSP_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 3,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* dsp_edma */
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[1] = PWRSTS_OFF_RET, /* dsp_l1 */
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[2] = PWRSTS_OFF_RET, /* dsp_l2 */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* dsp_edma */
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[1] = PWRSTS_OFF_RET, /* dsp_l1 */
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[2] = PWRSTS_OFF_RET, /* dsp_l2 */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* cam_54xx_pwrdm: Camera subsystem power domain */
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static struct powerdomain cam_54xx_pwrdm = {
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.name = "cam_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_CAM_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cam_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* cam_mem */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
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static struct powerdomain l3init_54xx_pwrdm = {
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.name = "l3init_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = OMAP54XX_PRM_L3INIT_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* l3init_bank1 */
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[1] = PWRSTS_OFF_RET, /* l3init_bank2 */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* l3init_bank1 */
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[1] = PWRSTS_OFF_RET, /* l3init_bank2 */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* gpu_54xx_pwrdm: 3D accelerator power domain */
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static struct powerdomain gpu_54xx_pwrdm = {
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.name = "gpu_pwrdm",
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.voltdm = { .name = "mm" },
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.prcm_offs = OMAP54XX_PRM_GPU_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* gpu_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* gpu_mem */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/* wkupaon_54xx_pwrdm: Wake-up power domain */
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static struct powerdomain wkupaon_54xx_pwrdm = {
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.name = "wkupaon_pwrdm",
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.voltdm = { .name = "wkup" },
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.prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* wkup_bank */
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},
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};
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/* iva_54xx_pwrdm: IVA-HD power domain */
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static struct powerdomain iva_54xx_pwrdm = {
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.name = "iva_pwrdm",
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.voltdm = { .name = "mm" },
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.prcm_offs = OMAP54XX_PRM_IVA_INST,
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.prcm_partition = OMAP54XX_PRM_PARTITION,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF,
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.banks = 4,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* hwa_mem */
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[1] = PWRSTS_OFF_RET, /* sl2_mem */
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[2] = PWRSTS_OFF_RET, /* tcm1_mem */
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[3] = PWRSTS_OFF_RET, /* tcm2_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET, /* hwa_mem */
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[1] = PWRSTS_OFF_RET, /* sl2_mem */
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[2] = PWRSTS_OFF_RET, /* tcm1_mem */
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[3] = PWRSTS_OFF_RET, /* tcm2_mem */
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},
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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};
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/*
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* The following power domains are not under SW control
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*
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* mpuaon
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* mmaon
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*/
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/* As powerdomains are added or removed above, this list must also be changed */
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static struct powerdomain *powerdomains_omap54xx[] __initdata = {
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&core_54xx_pwrdm,
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&abe_54xx_pwrdm,
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&coreaon_54xx_pwrdm,
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&dss_54xx_pwrdm,
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&cpu0_54xx_pwrdm,
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&cpu1_54xx_pwrdm,
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&emu_54xx_pwrdm,
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&mpu_54xx_pwrdm,
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&custefuse_54xx_pwrdm,
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&dsp_54xx_pwrdm,
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&cam_54xx_pwrdm,
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&l3init_54xx_pwrdm,
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&gpu_54xx_pwrdm,
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&wkupaon_54xx_pwrdm,
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&iva_54xx_pwrdm,
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NULL
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};
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void __init omap54xx_powerdomains_init(void)
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{
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pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
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pwrdm_register_pwrdms(powerdomains_omap54xx);
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pwrdm_complete_init();
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}
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