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710774e048
Add MT6779 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by: mtk01761 <wendell.lin@mediatek.com> Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Wendell Lin <wendell.lin@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6779-clk.h>
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static const struct mtk_gate_regs mfg_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_MFG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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static const struct mtk_gate mfg_clks[] = {
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GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
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};
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static int clk_mt6779_mfg_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
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mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
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clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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static const struct of_device_id of_match_clk_mt6779_mfg[] = {
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{ .compatible = "mediatek,mt6779-mfgcfg", },
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{}
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};
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static struct platform_driver clk_mt6779_mfg_drv = {
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.probe = clk_mt6779_mfg_probe,
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.driver = {
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.name = "clk-mt6779-mfg",
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.of_match_table = of_match_clk_mt6779_mfg,
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},
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};
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builtin_platform_driver(clk_mt6779_mfg_drv);
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