mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 15:43:59 +08:00
e7beeeec85
Commit 271707b1d8 ("mtd: nand: denali: max_banks calculation
changed in revision 5.1") added a revision check to support the
new max_banks encoding. Its git-log states "The encoding of
max_banks changed in Denali revision 5.1".
There are exceptional cases, for example, the revision register on
some UniPhier SoCs says the IP is 5.0 but the max_banks is encoded
in the new format.
This IP updates the resister specification from time to time (often
breaking the backward compatibility), but the revision number is not
incremented correctly.
The max_banks is not only the case that needs revision checking.
Let's allow to override an incorrect revision number.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
355 lines
10 KiB
C
355 lines
10 KiB
C
/*
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* NAND Flash Controller Device Driver
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* Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef __DENALI_H__
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#define __DENALI_H__
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#include <linux/bitops.h>
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#include <linux/mtd/nand.h>
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#define DEVICE_RESET 0x0
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#define DEVICE_RESET__BANK0 0x0001
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#define DEVICE_RESET__BANK1 0x0002
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#define DEVICE_RESET__BANK2 0x0004
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#define DEVICE_RESET__BANK3 0x0008
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#define TRANSFER_SPARE_REG 0x10
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#define TRANSFER_SPARE_REG__FLAG 0x0001
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#define LOAD_WAIT_CNT 0x20
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#define LOAD_WAIT_CNT__VALUE 0xffff
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#define PROGRAM_WAIT_CNT 0x30
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#define PROGRAM_WAIT_CNT__VALUE 0xffff
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#define ERASE_WAIT_CNT 0x40
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#define ERASE_WAIT_CNT__VALUE 0xffff
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#define INT_MON_CYCCNT 0x50
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#define INT_MON_CYCCNT__VALUE 0xffff
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#define RB_PIN_ENABLED 0x60
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#define RB_PIN_ENABLED__BANK0 0x0001
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#define RB_PIN_ENABLED__BANK1 0x0002
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#define RB_PIN_ENABLED__BANK2 0x0004
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#define RB_PIN_ENABLED__BANK3 0x0008
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#define MULTIPLANE_OPERATION 0x70
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#define MULTIPLANE_OPERATION__FLAG 0x0001
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#define MULTIPLANE_READ_ENABLE 0x80
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#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
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#define COPYBACK_DISABLE 0x90
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#define COPYBACK_DISABLE__FLAG 0x0001
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#define CACHE_WRITE_ENABLE 0xa0
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#define CACHE_WRITE_ENABLE__FLAG 0x0001
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#define CACHE_READ_ENABLE 0xb0
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#define CACHE_READ_ENABLE__FLAG 0x0001
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#define PREFETCH_MODE 0xc0
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#define PREFETCH_MODE__PREFETCH_EN 0x0001
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#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
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#define CHIP_ENABLE_DONT_CARE 0xd0
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#define CHIP_EN_DONT_CARE__FLAG 0x01
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#define ECC_ENABLE 0xe0
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#define ECC_ENABLE__FLAG 0x0001
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#define GLOBAL_INT_ENABLE 0xf0
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#define GLOBAL_INT_EN_FLAG 0x01
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#define WE_2_RE 0x100
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#define WE_2_RE__VALUE 0x003f
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#define ADDR_2_DATA 0x110
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#define ADDR_2_DATA__VALUE 0x003f
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#define RE_2_WE 0x120
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#define RE_2_WE__VALUE 0x003f
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#define ACC_CLKS 0x130
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#define ACC_CLKS__VALUE 0x000f
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#define NUMBER_OF_PLANES 0x140
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#define NUMBER_OF_PLANES__VALUE 0x0007
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#define PAGES_PER_BLOCK 0x150
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#define PAGES_PER_BLOCK__VALUE 0xffff
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#define DEVICE_WIDTH 0x160
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#define DEVICE_WIDTH__VALUE 0x0003
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#define DEVICE_MAIN_AREA_SIZE 0x170
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#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
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#define DEVICE_SPARE_AREA_SIZE 0x180
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#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
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#define TWO_ROW_ADDR_CYCLES 0x190
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#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
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#define MULTIPLANE_ADDR_RESTRICT 0x1a0
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#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
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#define ECC_CORRECTION 0x1b0
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#define ECC_CORRECTION__VALUE 0x001f
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#define READ_MODE 0x1c0
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#define READ_MODE__VALUE 0x000f
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#define WRITE_MODE 0x1d0
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#define WRITE_MODE__VALUE 0x000f
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#define COPYBACK_MODE 0x1e0
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#define COPYBACK_MODE__VALUE 0x000f
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#define RDWR_EN_LO_CNT 0x1f0
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#define RDWR_EN_LO_CNT__VALUE 0x001f
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#define RDWR_EN_HI_CNT 0x200
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#define RDWR_EN_HI_CNT__VALUE 0x001f
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#define MAX_RD_DELAY 0x210
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#define MAX_RD_DELAY__VALUE 0x000f
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#define CS_SETUP_CNT 0x220
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#define CS_SETUP_CNT__VALUE 0x001f
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#define SPARE_AREA_SKIP_BYTES 0x230
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#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
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#define SPARE_AREA_MARKER 0x240
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#define SPARE_AREA_MARKER__VALUE 0xffff
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#define DEVICES_CONNECTED 0x250
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#define DEVICES_CONNECTED__VALUE 0x0007
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#define DIE_MASK 0x260
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#define DIE_MASK__VALUE 0x00ff
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#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
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#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
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#define WRITE_PROTECT 0x280
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#define WRITE_PROTECT__FLAG 0x0001
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#define RE_2_RE 0x290
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#define RE_2_RE__VALUE 0x003f
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#define MANUFACTURER_ID 0x300
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#define MANUFACTURER_ID__VALUE 0x00ff
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#define DEVICE_ID 0x310
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#define DEVICE_ID__VALUE 0x00ff
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#define DEVICE_PARAM_0 0x320
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#define DEVICE_PARAM_0__VALUE 0x00ff
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#define DEVICE_PARAM_1 0x330
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#define DEVICE_PARAM_1__VALUE 0x00ff
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#define DEVICE_PARAM_2 0x340
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#define DEVICE_PARAM_2__VALUE 0x00ff
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#define LOGICAL_PAGE_DATA_SIZE 0x350
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#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
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#define LOGICAL_PAGE_SPARE_SIZE 0x360
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#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
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#define REVISION 0x370
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#define REVISION__VALUE 0xffff
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#define ONFI_DEVICE_FEATURES 0x380
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#define ONFI_DEVICE_FEATURES__VALUE 0x003f
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#define ONFI_OPTIONAL_COMMANDS 0x390
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#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
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#define ONFI_TIMING_MODE 0x3a0
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#define ONFI_TIMING_MODE__VALUE 0x003f
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#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
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#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
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#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
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#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
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#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
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#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
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#define FEATURES 0x3f0
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#define FEATURES__N_BANKS 0x0003
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#define FEATURES__ECC_MAX_ERR 0x003c
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#define FEATURES__DMA 0x0040
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#define FEATURES__CMD_DMA 0x0080
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#define FEATURES__PARTITION 0x0100
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#define FEATURES__XDMA_SIDEBAND 0x0200
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#define FEATURES__GPREG 0x0400
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#define FEATURES__INDEX_ADDR 0x0800
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#define TRANSFER_MODE 0x400
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#define TRANSFER_MODE__VALUE 0x0003
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#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
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#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
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/* bit[1:0] is used differently depending on IP version */
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#define INTR__ECC_UNCOR_ERR 0x0001 /* new IP */
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#define INTR__ECC_TRANSACTION_DONE 0x0001 /* old IP */
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#define INTR__ECC_ERR 0x0002 /* old IP */
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#define INTR__DMA_CMD_COMP 0x0004
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#define INTR__TIME_OUT 0x0008
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#define INTR__PROGRAM_FAIL 0x0010
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#define INTR__ERASE_FAIL 0x0020
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#define INTR__LOAD_COMP 0x0040
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#define INTR__PROGRAM_COMP 0x0080
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#define INTR__ERASE_COMP 0x0100
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#define INTR__PIPE_CPYBCK_CMD_COMP 0x0200
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#define INTR__LOCKED_BLK 0x0400
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#define INTR__UNSUP_CMD 0x0800
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#define INTR__INT_ACT 0x1000
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#define INTR__RST_COMP 0x2000
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#define INTR__PIPE_CMD_ERR 0x4000
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#define INTR__PAGE_XFER_INC 0x8000
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#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
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#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
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#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
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#define ECC_THRESHOLD 0x600
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#define ECC_THRESHOLD__VALUE 0x03ff
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#define ECC_ERROR_BLOCK_ADDRESS 0x610
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#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
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#define ECC_ERROR_PAGE_ADDRESS 0x620
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#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
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#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
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#define ECC_ERROR_ADDRESS 0x630
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#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
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#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
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#define ERR_CORRECTION_INFO 0x640
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#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
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#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
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#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
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#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
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#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
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#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
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#define ECC_COR_INFO__MAX_ERRORS 0x007f
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#define ECC_COR_INFO__UNCOR_ERR 0x0080
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#define DMA_ENABLE 0x700
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#define DMA_ENABLE__FLAG 0x0001
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#define IGNORE_ECC_DONE 0x710
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#define IGNORE_ECC_DONE__FLAG 0x0001
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#define DMA_INTR 0x720
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#define DMA_INTR_EN 0x730
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#define DMA_INTR__TARGET_ERROR 0x0001
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#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
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#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
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#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
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#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
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#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
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#define TARGET_ERR_ADDR_LO 0x740
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#define TARGET_ERR_ADDR_LO__VALUE 0xffff
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#define TARGET_ERR_ADDR_HI 0x750
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#define TARGET_ERR_ADDR_HI__VALUE 0xffff
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#define CHNL_ACTIVE 0x760
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#define CHNL_ACTIVE__CHANNEL0 0x0001
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#define CHNL_ACTIVE__CHANNEL1 0x0002
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#define CHNL_ACTIVE__CHANNEL2 0x0004
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#define CHNL_ACTIVE__CHANNEL3 0x0008
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#define FAIL 1 /*failed flag*/
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#define PASS 0 /*success flag*/
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#define CLK_X 5
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#define CLK_MULTI 4
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#define ONFI_BLOOM_TIME 1
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#define MODE5_WORKAROUND 0
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#define MODE_00 0x00000000
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#define MODE_01 0x04000000
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#define MODE_10 0x08000000
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#define MODE_11 0x0C000000
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#define ECC_SECTOR_SIZE 512
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struct nand_buf {
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int head;
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int tail;
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uint8_t *buf;
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dma_addr_t dma_buf;
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};
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#define INTEL_CE4100 1
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#define INTEL_MRST 2
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#define DT 3
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struct denali_nand_info {
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struct nand_chip nand;
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int flash_bank; /* currently selected chip */
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int status;
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int platform;
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struct nand_buf buf;
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struct device *dev;
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int total_used_banks;
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int page;
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void __iomem *flash_reg; /* Register Interface */
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void __iomem *flash_mem; /* Host Data/Command Interface */
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/* elements used by ISR */
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struct completion complete;
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spinlock_t irq_lock;
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uint32_t irq_status;
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int irq;
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int devnum; /* represent how many nands connected */
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int bbtskipbytes;
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int max_banks;
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unsigned int revision;
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unsigned int caps;
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};
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#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
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#define DENALI_CAP_DMA_64BIT BIT(1)
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extern int denali_init(struct denali_nand_info *denali);
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extern void denali_remove(struct denali_nand_info *denali);
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#endif /* __DENALI_H__ */
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