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The at91rm9200 SoC embeds a Memory Controller block which is used to configure several aspects of the platform: - AHB/APB Bus behavior - SDRAM Controller - EBI (External Bus Interface) and SMC (Static Memory Controller) config Those registers might be accessed by different drivers, hence we need to define it as a syscon device. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
145 lines
4.8 KiB
C
145 lines
4.8 KiB
C
/*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
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* registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
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#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
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/* Memory Controller */
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#define AT91_MC_RCR 0x00
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#define AT91_MC_RCB BIT(0)
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#define AT91_MC_ASR 0x04
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#define AT91_MC_UNADD BIT(0)
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#define AT91_MC_MISADD BIT(1)
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#define AT91_MC_ABTSZ GENMASK(9, 8)
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#define AT91_MC_ABTSZ_BYTE (0 << 8)
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#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
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#define AT91_MC_ABTSZ_WORD (2 << 8)
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#define AT91_MC_ABTTYP GENMASK(11, 10)
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#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
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#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
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#define AT91_MC_ABTTYP_FETCH (2 << 10)
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#define AT91_MC_MST(n) BIT(16 + (n))
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#define AT91_MC_SVMST(n) BIT(24 + (n))
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#define AT91_MC_AASR 0x08
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#define AT91_MC_MPR 0x0c
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#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
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/* External Bus Interface (EBI) registers */
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#define AT91_MC_EBI_CSA 0x60
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#define AT91_MC_EBI_CS(n) BIT(x)
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#define AT91_MC_EBI_NUM_CS 8
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#define AT91_MC_EBI_CFGR 0x64
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#define AT91_MC_EBI_DBPUC BIT(0)
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/* Static Memory Controller (SMC) registers */
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#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
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#define AT91_MC_SMC_NWS GENMASK(6, 0)
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#define AT91_MC_SMC_NWS_(x) ((x) << 0)
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#define AT91_MC_SMC_WSEN BIT(7)
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#define AT91_MC_SMC_TDF GENMASK(11, 8)
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#define AT91_MC_SMC_TDF_(x) ((x) << 8)
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#define AT91_MC_SMC_TDF_MAX 0xf
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#define AT91_MC_SMC_BAT BIT(12)
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#define AT91_MC_SMC_DBW GENMASK(14, 13)
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#define AT91_MC_SMC_DBW_16 (1 << 13)
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#define AT91_MC_SMC_DBW_8 (2 << 13)
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#define AT91_MC_SMC_DPR BIT(15)
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#define AT91_MC_SMC_ACSS GENMASK(17, 16)
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#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
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#define AT91_MC_SMC_ACSS_MAX 3
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#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
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#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
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#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
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#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
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#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
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/* SDRAM Controller registers */
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#define AT91_MC_SDRAMC_MR 0x90
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#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
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#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
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#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
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#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
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#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
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#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
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#define AT91_MC_SDRAMC_DBW_16 BIT(4)
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#define AT91_MC_SDRAMC_TR 0x94
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#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
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#define AT91_MC_SDRAMC_CR 0x98
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#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
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#define AT91_MC_SDRAMC_NC_8 (0 << 0)
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#define AT91_MC_SDRAMC_NC_9 (1 << 0)
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#define AT91_MC_SDRAMC_NC_10 (2 << 0)
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#define AT91_MC_SDRAMC_NC_11 (3 << 0)
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#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
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#define AT91_MC_SDRAMC_NR_11 (0 << 2)
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#define AT91_MC_SDRAMC_NR_12 (1 << 2)
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#define AT91_MC_SDRAMC_NR_13 (2 << 2)
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#define AT91_MC_SDRAMC_NB BIT(4)
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#define AT91_MC_SDRAMC_NB_2 (0 << 4)
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#define AT91_MC_SDRAMC_NB_4 (1 << 4)
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#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
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#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
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#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
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#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
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#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
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#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
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#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
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#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
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#define AT91_MC_SDRAMC_SRR 0x9c
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#define AT91_MC_SDRAMC_SRCB BIT(0)
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#define AT91_MC_SDRAMC_LPR 0xa0
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#define AT91_MC_SDRAMC_LPCB BIT(0)
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#define AT91_MC_SDRAMC_IER 0xa4
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#define AT91_MC_SDRAMC_IDR 0xa8
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#define AT91_MC_SDRAMC_IMR 0xac
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#define AT91_MC_SDRAMC_ISR 0xb0
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#define AT91_MC_SDRAMC_RES BIT(0)
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/* Burst Flash Controller register */
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#define AT91_MC_BFC_MR 0xc0
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#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
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#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
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#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
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#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
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#define AT91_MC_BFC_BFCC GENMASK(3, 2)
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#define AT91_MC_BFC_BFCC_MCK (1 << 2)
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#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
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#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
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#define AT91_MC_BFC_AVL GENMASK(7, 4)
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#define AT91_MC_BFC_PAGES GENMASK(10, 8)
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#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
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#define AT91_MC_BFC_PAGES_16 (1 << 8)
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#define AT91_MC_BFC_PAGES_32 (2 << 8)
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#define AT91_MC_BFC_PAGES_64 (3 << 8)
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#define AT91_MC_BFC_PAGES_128 (4 << 8)
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#define AT91_MC_BFC_PAGES_256 (5 << 8)
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#define AT91_MC_BFC_PAGES_512 (6 << 8)
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#define AT91_MC_BFC_PAGES_1024 (7 << 8)
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#define AT91_MC_BFC_OEL GENMASK(13, 12)
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#define AT91_MC_BFC_BAAEN BIT(16)
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#define AT91_MC_BFC_BFOEH BIT(17)
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#define AT91_MC_BFC_MUXEN BIT(18)
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#define AT91_MC_BFC_RDYEN BIT(19)
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#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
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