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fa31b3cb2a
The xHCI controller on various Intel SoCs has an extended cap mmio-range which contains registers to control the muxing to the xHCI (host mode) or the dwc3 (device mode) and vbus-detection for the otg usb-phy. Having a role-sw driver included in the xHCI code (under drivers/usb/host) is not desirable. So this commit adds a simple handler for this extended capability, which creates a platform device with the caps mmio region as resource, this allows us to write a separate platform role-sw driver for the role-switch. Note this commit adds a call to the new xhci_ext_cap_init() function to xhci_pci_probe(), it is added here because xhci_ext_cap_init() must be called only once. If in the future we also want to handle ext-caps on non pci xHCI HCDs from xhci_ext_cap_init() a call to it should also be added to other bus probe paths. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*/
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/* Up to 16 ms to halt an HC */
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#define XHCI_MAX_HALT_USEC (16*1000)
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/* HC not running - set to 1 when run/stop bit is cleared. */
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#define XHCI_STS_HALT (1<<0)
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/* HCCPARAMS offset from PCI base address */
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#define XHCI_HCC_PARAMS_OFFSET 0x10
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/* HCCPARAMS contains the first extended capability pointer */
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#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
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/* Command and Status registers offset from the Operational Registers address */
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#define XHCI_CMD_OFFSET 0x00
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#define XHCI_STS_OFFSET 0x04
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#define XHCI_MAX_EXT_CAPS 50
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/* Capability Register */
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/* bits 7:0 - how long is the Capabilities register */
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#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
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/* Extended capability register fields */
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#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
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#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
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#define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
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/* Extended capability IDs - ID 0 reserved */
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#define XHCI_EXT_CAPS_LEGACY 1
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#define XHCI_EXT_CAPS_PROTOCOL 2
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#define XHCI_EXT_CAPS_PM 3
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#define XHCI_EXT_CAPS_VIRT 4
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#define XHCI_EXT_CAPS_ROUTE 5
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/* IDs 6-9 reserved */
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#define XHCI_EXT_CAPS_DEBUG 10
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/* Vendor caps */
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#define XHCI_EXT_CAPS_VENDOR_INTEL 192
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/* USB Legacy Support Capability - section 7.1.1 */
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#define XHCI_HC_BIOS_OWNED (1 << 16)
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#define XHCI_HC_OS_OWNED (1 << 24)
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/* USB Legacy Support Capability - section 7.1.1 */
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/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
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#define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
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/* USB Legacy Support Control and Status Register - section 7.1.2 */
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/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
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#define XHCI_LEGACY_CONTROL_OFFSET (0x04)
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/* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
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#define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
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#define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
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/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
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#define XHCI_L1C (1 << 16)
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/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
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#define XHCI_HLC (1 << 19)
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#define XHCI_BLC (1 << 20)
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/* command register values to disable interrupts and halt the HC */
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/* start/stop HC execution - do not write unless HC is halted*/
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#define XHCI_CMD_RUN (1 << 0)
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/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
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#define XHCI_CMD_EIE (1 << 2)
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/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
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#define XHCI_CMD_HSEIE (1 << 3)
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/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
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#define XHCI_CMD_EWE (1 << 10)
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#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
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/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
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#define XHCI_STS_CNR (1 << 11)
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#include <linux/io.h>
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/**
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* Find the offset of the extended capabilities with capability ID id.
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*
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* @base PCI MMIO registers base address.
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* @start address at which to start looking, (0 or HCC_PARAMS to start at
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* beginning of list)
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* @id Extended capability ID to search for, or 0 for the next
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* capability
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*
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* Returns the offset of the next matching extended capability structure.
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* Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
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* and this provides a way to find them all.
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*/
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static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
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{
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u32 val;
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u32 next;
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u32 offset;
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offset = start;
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if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
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val = readl(base + XHCI_HCC_PARAMS_OFFSET);
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if (val == ~0)
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return 0;
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offset = XHCI_HCC_EXT_CAPS(val) << 2;
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if (!offset)
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return 0;
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}
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do {
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val = readl(base + offset);
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if (val == ~0)
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return 0;
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if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
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return offset;
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next = XHCI_EXT_CAPS_NEXT(val);
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offset += next << 2;
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} while (next);
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return 0;
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}
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