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https://github.com/edk2-porting/linux-next.git
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edabd38e1a
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
/*
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* arch/arm/mach-dove/irq.c
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*
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* Dove IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <plat/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/pm.h>
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#include <mach/bridge-regs.h>
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#include "common.h"
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static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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int irqoff;
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BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
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irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
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3 + irq - IRQ_DOVE_GPIO_24_31;
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orion_gpio_irq_handler(irqoff << 3);
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if (irq == IRQ_DOVE_HIGH_GPIO) {
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orion_gpio_irq_handler(40);
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orion_gpio_irq_handler(48);
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orion_gpio_irq_handler(56);
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}
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}
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static void pmu_irq_mask(unsigned int irq)
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{
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int pin = irq_to_pmu(irq);
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u32 u;
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u = readl(PMU_INTERRUPT_MASK);
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u &= ~(1 << (pin & 31));
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writel(u, PMU_INTERRUPT_MASK);
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}
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static void pmu_irq_unmask(unsigned int irq)
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{
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int pin = irq_to_pmu(irq);
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u32 u;
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u = readl(PMU_INTERRUPT_MASK);
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u |= 1 << (pin & 31);
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writel(u, PMU_INTERRUPT_MASK);
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}
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static void pmu_irq_ack(unsigned int irq)
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{
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int pin = irq_to_pmu(irq);
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u32 u;
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u = ~(1 << (pin & 31));
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writel(u, PMU_INTERRUPT_CAUSE);
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}
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static struct irq_chip pmu_irq_chip = {
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.name = "pmu_irq",
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.mask = pmu_irq_mask,
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.unmask = pmu_irq_unmask,
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.ack = pmu_irq_ack,
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};
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static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
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cause &= readl(PMU_INTERRUPT_MASK);
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if (cause == 0) {
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do_bad_IRQ(irq, desc);
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return;
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}
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for (irq = 0; irq < NR_PMU_IRQS; irq++) {
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if (!(cause & (1 << irq)))
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continue;
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irq = pmu_to_irq(irq);
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desc = irq_desc + irq;
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desc_handle_irq(irq, desc);
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}
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}
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void __init dove_init_irq(void)
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{
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int i;
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orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
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orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
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/*
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* Mask and clear GPIO IRQ interrupts.
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*/
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writel(0, GPIO_LEVEL_MASK(0));
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writel(0, GPIO_EDGE_MASK(0));
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writel(0, GPIO_EDGE_CAUSE(0));
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/*
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* Mask and clear PMU interrupts
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*/
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writel(0, PMU_INTERRUPT_MASK);
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writel(0, PMU_INTERRUPT_CAUSE);
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for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
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set_irq_chip(i, &orion_gpio_irq_chip);
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set_irq_handler(i, handle_level_irq);
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irq_desc[i].status |= IRQ_LEVEL;
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
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set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
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set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
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set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
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set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
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for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
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set_irq_chip(i, &pmu_irq_chip);
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set_irq_handler(i, handle_level_irq);
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irq_desc[i].status |= IRQ_LEVEL;
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
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}
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