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3008ddbe06
This patch adds max14577 core/irq driver to support MUIC(Micro USB IC) device and charger device and support irq domain method to control internal interrupt of max14577 device. Also, this patch supports DT binding with max14577_i2c_parse_dt(). The MAXIM 14577 chip contains Micro-USB Interface Circuit and Li+ Battery Charger. It contains accessory and USB charger detection logic. It supports USB 2.0 Hi-Speed, UART and stereo audio signals over Micro-USB connector. The battery charger is compliant with the USB Battery Charging Specification Revision 1.1. It has also SFOUT LDO output for powering USB devices. Reviewed-by: Mark Brown <broonie@linaro.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
331 lines
10 KiB
C
331 lines
10 KiB
C
/*
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* max14577-private.h - Common API for the Maxim 14577 internal sub chip
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*
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* Copyright (C) 2013 Samsung Electrnoics
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* Chanwoo Choi <cw00.choi@samsung.com>
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* Krzysztof Kozlowski <k.kozlowski@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAX14577_PRIVATE_H__
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#define __MAX14577_PRIVATE_H__
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#define MAX14577_REG_INVALID (0xff)
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/* Slave addr = 0x4A: Interrupt */
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enum max14577_reg {
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MAX14577_REG_DEVICEID = 0x00,
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MAX14577_REG_INT1 = 0x01,
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MAX14577_REG_INT2 = 0x02,
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MAX14577_REG_INT3 = 0x03,
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MAX14577_REG_STATUS1 = 0x04,
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MAX14577_REG_STATUS2 = 0x05,
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MAX14577_REG_STATUS3 = 0x06,
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MAX14577_REG_INTMASK1 = 0x07,
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MAX14577_REG_INTMASK2 = 0x08,
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MAX14577_REG_INTMASK3 = 0x09,
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MAX14577_REG_CDETCTRL1 = 0x0A,
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MAX14577_REG_RFU = 0x0B,
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MAX14577_REG_CONTROL1 = 0x0C,
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MAX14577_REG_CONTROL2 = 0x0D,
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MAX14577_REG_CONTROL3 = 0x0E,
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MAX14577_REG_CHGCTRL1 = 0x0F,
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MAX14577_REG_CHGCTRL2 = 0x10,
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MAX14577_REG_CHGCTRL3 = 0x11,
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MAX14577_REG_CHGCTRL4 = 0x12,
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MAX14577_REG_CHGCTRL5 = 0x13,
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MAX14577_REG_CHGCTRL6 = 0x14,
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MAX14577_REG_CHGCTRL7 = 0x15,
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MAX14577_REG_END,
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};
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/* Slave addr = 0x4A: MUIC */
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enum max14577_muic_reg {
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MAX14577_MUIC_REG_STATUS1 = 0x04,
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MAX14577_MUIC_REG_STATUS2 = 0x05,
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MAX14577_MUIC_REG_CONTROL1 = 0x0C,
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MAX14577_MUIC_REG_CONTROL3 = 0x0E,
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MAX14577_MUIC_REG_END,
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};
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enum max14577_muic_charger_type {
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MAX14577_CHARGER_TYPE_NONE = 0,
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MAX14577_CHARGER_TYPE_USB,
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MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT,
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MAX14577_CHARGER_TYPE_DEDICATED_CHG,
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MAX14577_CHARGER_TYPE_SPECIAL_500MA,
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MAX14577_CHARGER_TYPE_SPECIAL_1A,
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MAX14577_CHARGER_TYPE_RESERVED,
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MAX14577_CHARGER_TYPE_DEAD_BATTERY = 7,
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};
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/* MAX14577 interrupts */
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#define INT1_ADC_MASK (0x1 << 0)
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#define INT1_ADCLOW_MASK (0x1 << 1)
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#define INT1_ADCERR_MASK (0x1 << 2)
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#define INT2_CHGTYP_MASK (0x1 << 0)
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#define INT2_CHGDETRUN_MASK (0x1 << 1)
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#define INT2_DCDTMR_MASK (0x1 << 2)
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#define INT2_DBCHG_MASK (0x1 << 3)
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#define INT2_VBVOLT_MASK (0x1 << 4)
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#define INT3_EOC_MASK (0x1 << 0)
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#define INT3_CGMBC_MASK (0x1 << 1)
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#define INT3_OVP_MASK (0x1 << 2)
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#define INT3_MBCCHGERR_MASK (0x1 << 3)
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/* MAX14577 DEVICE ID register */
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#define DEVID_VENDORID_SHIFT 0
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#define DEVID_DEVICEID_SHIFT 3
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#define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT)
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#define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT)
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/* MAX14577 STATUS1 register */
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#define STATUS1_ADC_SHIFT 0
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#define STATUS1_ADCLOW_SHIFT 5
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#define STATUS1_ADCERR_SHIFT 6
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#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
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#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
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/* MAX14577 STATUS2 register */
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#define STATUS2_CHGTYP_SHIFT 0
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#define STATUS2_CHGDETRUN_SHIFT 3
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#define STATUS2_DCDTMR_SHIFT 4
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#define STATUS2_DBCHG_SHIFT 5
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#define STATUS2_VBVOLT_SHIFT 6
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#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
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#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
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#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
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#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
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#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
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/* MAX14577 CONTROL1 register */
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#define COMN1SW_SHIFT 0
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#define COMP2SW_SHIFT 3
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#define MICEN_SHIFT 6
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#define IDBEN_SHIFT 7
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#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
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#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
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#define MICEN_MASK (0x1 << MICEN_SHIFT)
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#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
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#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
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#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
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| (1 << COMN1SW_SHIFT))
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#define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
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| (2 << COMN1SW_SHIFT))
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#define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \
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| (3 << COMN1SW_SHIFT))
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#define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
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| (0 << COMN1SW_SHIFT))
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/* MAX14577 CONTROL2 register */
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#define CTRL2_LOWPWR_SHIFT (0)
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#define CTRL2_ADCEN_SHIFT (1)
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#define CTRL2_CPEN_SHIFT (2)
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#define CTRL2_SFOUTASRT_SHIFT (3)
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#define CTRL2_SFOUTORD_SHIFT (4)
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#define CTRL2_ACCDET_SHIFT (5)
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#define CTRL2_USBCPINT_SHIFT (6)
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#define CTRL2_RCPS_SHIFT (7)
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#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
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#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT)
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#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
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#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT)
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#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT)
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#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
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#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT)
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#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT)
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#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
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(0 << CTRL2_LOWPWR_SHIFT))
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#define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
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(1 << CTRL2_LOWPWR_SHIFT))
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/* MAX14577 CONTROL3 register */
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#define CTRL3_JIGSET_SHIFT 0
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#define CTRL3_BOOTSET_SHIFT 2
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#define CTRL3_ADCDBSET_SHIFT 4
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#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
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#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT)
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#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
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/* Slave addr = 0x4A: Charger */
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enum max14577_charger_reg {
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MAX14577_CHG_REG_STATUS3 = 0x06,
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MAX14577_CHG_REG_CHG_CTRL1 = 0x0F,
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MAX14577_CHG_REG_CHG_CTRL2 = 0x10,
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MAX14577_CHG_REG_CHG_CTRL3 = 0x11,
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MAX14577_CHG_REG_CHG_CTRL4 = 0x12,
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MAX14577_CHG_REG_CHG_CTRL5 = 0x13,
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MAX14577_CHG_REG_CHG_CTRL6 = 0x14,
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MAX14577_CHG_REG_CHG_CTRL7 = 0x15,
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MAX14577_CHG_REG_END,
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};
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/* MAX14577 STATUS3 register */
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#define STATUS3_EOC_SHIFT 0
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#define STATUS3_CGMBC_SHIFT 1
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#define STATUS3_OVP_SHIFT 2
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#define STATUS3_MBCCHGERR_SHIFT 3
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#define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT)
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#define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT)
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#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
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#define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT)
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/* MAX14577 CDETCTRL1 register */
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#define CDETCTRL1_CHGDETEN_SHIFT 0
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#define CDETCTRL1_CHGTYPMAN_SHIFT 1
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#define CDETCTRL1_DCDEN_SHIFT 2
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#define CDETCTRL1_DCD2SCT_SHIFT 3
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#define CDETCTRL1_DCHKTM_SHIFT 4
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#define CDETCTRL1_DBEXIT_SHIFT 5
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#define CDETCTRL1_DBIDLE_SHIFT 6
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#define CDETCTRL1_CDPDET_SHIFT 7
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#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT)
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#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT)
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#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT)
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#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
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/* MAX14577 CHGCTRL1 register */
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#define CHGCTRL1_TCHW_SHIFT 4
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#define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT)
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/* MAX14577 CHGCTRL2 register */
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#define CHGCTRL2_MBCHOSTEN_SHIFT 6
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#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT)
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#define CHGCTRL2_VCHGR_RC_SHIFT 7
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#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT)
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/* MAX14577 CHGCTRL3 register */
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#define CHGCTRL3_MBCCVWRC_SHIFT 0
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#define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
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/* MAX14577 CHGCTRL4 register */
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#define CHGCTRL4_MBCICHWRCH_SHIFT 0
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#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
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#define CHGCTRL4_MBCICHWRCL_SHIFT 4
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#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT)
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/* MAX14577 CHGCTRL5 register */
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#define CHGCTRL5_EOCS_SHIFT 0
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#define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT)
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/* MAX14577 CHGCTRL6 register */
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#define CHGCTRL6_AUTOSTOP_SHIFT 5
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#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT)
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/* MAX14577 CHGCTRL7 register */
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#define CHGCTRL7_OTPCGHCVS_SHIFT 0
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#define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
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/* MAX14577 regulator current limits (as in CHGCTRL4 register), uA */
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#define MAX14577_REGULATOR_CURRENT_LIMIT_MIN 90000
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#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_START 200000
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#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000
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#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000
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/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
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#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
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enum max14577_irq_source {
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MAX14577_IRQ_INT1 = 0,
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MAX14577_IRQ_INT2,
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MAX14577_IRQ_INT3,
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MAX14577_IRQ_REGS_NUM,
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};
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enum max14577_irq {
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/* INT1 */
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MAX14577_IRQ_INT1_ADC,
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MAX14577_IRQ_INT1_ADCLOW,
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MAX14577_IRQ_INT1_ADCERR,
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/* INT2 */
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MAX14577_IRQ_INT2_CHGTYP,
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MAX14577_IRQ_INT2_CHGDETRUN,
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MAX14577_IRQ_INT2_DCDTMR,
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MAX14577_IRQ_INT2_DBCHG,
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MAX14577_IRQ_INT2_VBVOLT,
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/* INT3 */
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MAX14577_IRQ_INT3_EOC,
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MAX14577_IRQ_INT3_CGMBC,
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MAX14577_IRQ_INT3_OVP,
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MAX14577_IRQ_INT3_MBCCHGERR,
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MAX14577_IRQ_NUM,
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};
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struct max14577 {
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struct device *dev;
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struct i2c_client *i2c; /* Slave addr = 0x4A */
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_data;
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int irq;
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/* Device ID */
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u8 vendor_id; /* Vendor Identification */
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u8 device_id; /* Chip Version */
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};
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/* MAX14577 shared regmap API function */
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static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest)
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{
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unsigned int val;
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int ret;
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ret = regmap_read(map, reg, &val);
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*dest = val;
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return ret;
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}
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static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf,
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int count)
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{
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return regmap_bulk_read(map, reg, buf, count);
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}
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static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value)
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{
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return regmap_write(map, reg, value);
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}
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static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf,
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int count)
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{
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return regmap_bulk_write(map, reg, buf, count);
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}
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static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask,
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u8 val)
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{
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return regmap_update_bits(map, reg, mask, val);
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}
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#endif /* __MAX14577_PRIVATE_H__ */
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