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5a9ebe9599
Since technically it's not powerpc arch-specific. Also rename it sec2 to differentiate it from its incompatible successor, the SEC 4. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
69 lines
2.7 KiB
Plaintext
69 lines
2.7 KiB
Plaintext
Freescale SoC SEC Security Engines versions 2.x-3.x
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Required properties:
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- compatible : Should contain entries for this and backward compatible
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SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
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- reg : Offset and length of the register set for the device
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- interrupts : the SEC's interrupt number
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- fsl,num-channels : An integer representing the number of channels
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available.
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- fsl,channel-fifo-len : An integer representing the number of
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descriptor pointers each channel fetch fifo can hold.
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- fsl,exec-units-mask : The bitmask representing what execution units
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(EUs) are available. It's a single 32-bit cell. EU information
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should be encoded following the SEC's Descriptor Header Dword
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EU_SEL0 field documentation, i.e. as follows:
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bit 0 = reserved - should be 0
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bit 1 = set if SEC has the ARC4 EU (AFEU)
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bit 2 = set if SEC has the DES/3DES EU (DEU)
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bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
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bit 4 = set if SEC has the random number generator EU (RNG)
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bit 5 = set if SEC has the public key EU (PKEU)
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bit 6 = set if SEC has the AES EU (AESU)
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bit 7 = set if SEC has the Kasumi EU (KEU)
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bit 8 = set if SEC has the CRC EU (CRCU)
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bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
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remaining bits are reserved for future SEC EUs.
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- fsl,descriptor-types-mask : The bitmask representing what descriptors
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are available. It's a single 32-bit cell. Descriptor type information
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should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
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field documentation, i.e. as follows:
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bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
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bit 1 = set if SEC supports the ipsec_esp descriptor type
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bit 2 = set if SEC supports the common_nonsnoop desc. type
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bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
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bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
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bit 5 = set if SEC supports the srtp descriptor type
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bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
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bit 7 = set if SEC supports the pkeu_assemble descriptor type
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bit 8 = set if SEC supports the aesu_key_expand_output desc.type
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bit 9 = set if SEC supports the pkeu_ptmul descriptor type
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bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
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bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
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..and so on and so forth.
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Optional properties:
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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Example:
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/* MPC8548E */
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crypto@30000 {
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compatible = "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <29 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xfe>;
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fsl,descriptor-types-mask = <0x12b0ebf>;
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};
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