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4d4e58de32
Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/*
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* Renesas SuperH DMA Engine support
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*
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __DMA_SHDMA_H
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#define __DMA_SHDMA_H
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#define SH_DMAC_MAX_CHANNELS 20
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#define SH_DMA_SLAVE_NUMBER 256
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#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
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struct device;
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enum dmae_pm_state {
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DMAE_PM_ESTABLISHED,
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DMAE_PM_BUSY,
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DMAE_PM_PENDING,
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};
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struct sh_dmae_chan {
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spinlock_t desc_lock; /* Descriptor operation lock */
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struct list_head ld_queue; /* Link descriptors queue */
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struct list_head ld_free; /* Link descriptors free */
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struct dma_chan common; /* DMA common channel */
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struct device *dev; /* Channel device */
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struct tasklet_struct tasklet; /* Tasklet */
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int descs_allocated; /* desc count */
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int xmit_shift; /* log_2(bytes_per_xfer) */
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int irq;
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int id; /* Raw id of this channel */
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u32 __iomem *base;
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char dev_id[16]; /* unique name per DMAC of channel */
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int pm_error;
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enum dmae_pm_state pm_state;
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};
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struct sh_dmae_device {
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struct dma_device common;
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struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS];
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struct sh_dmae_pdata *pdata;
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struct list_head node;
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u32 __iomem *chan_reg;
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u16 __iomem *dmars;
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unsigned int chcr_offset;
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u32 chcr_ie_bit;
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};
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#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
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#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
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#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
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#define to_sh_dev(chan) container_of(chan->common.device,\
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struct sh_dmae_device, common)
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#endif /* __DMA_SHDMA_H */
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