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7f4b04614a
Currently cpufreq frequency table has two fields: frequency and driver_data. driver_data is only for drivers' internal use and cpufreq core shouldn't use it at all. But with the introduction of BOOST frequencies, this assumption was broken and we started using it as a flag instead. There are two problems due to this: - It is against the description of this field, as driver's data is used by the core now. - if drivers fill it with -3 for any frequency, then those frequencies are never considered by cpufreq core as it is exactly same as value of CPUFREQ_BOOST_FREQ, i.e. ~2. The best way to get this fixed is by creating another field flags which will be used for such flags. This patch does that. Along with that various drivers need modifications due to the change of struct cpufreq_frequency_table. Reviewed-by: Gautham R Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
141 lines
3.0 KiB
C
141 lines
3.0 KiB
C
/*
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* sc520_freq.c: cpufreq driver for the AMD Elan sc520
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*
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* Copyright (C) 2005 Sean Young <sean@mess.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Based on elanfreq.c
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*
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* 2005-03-30: - initial revision
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/cpufreq.h>
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#include <linux/timex.h>
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#include <linux/io.h>
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#include <asm/cpu_device_id.h>
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#include <asm/msr.h>
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#define MMCR_BASE 0xfffef000 /* The default base address */
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#define OFFS_CPUCTL 0x2 /* CPU Control Register */
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static __u8 __iomem *cpuctl;
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#define PFX "sc520_freq: "
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static struct cpufreq_frequency_table sc520_freq_table[] = {
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{0, 0x01, 100000},
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{0, 0x02, 133000},
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{0, 0, CPUFREQ_TABLE_END},
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};
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static unsigned int sc520_freq_get_cpu_frequency(unsigned int cpu)
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{
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u8 clockspeed_reg = *cpuctl;
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switch (clockspeed_reg & 0x03) {
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default:
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printk(KERN_ERR PFX "error: cpuctl register has unexpected "
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"value %02x\n", clockspeed_reg);
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case 0x01:
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return 100000;
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case 0x02:
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return 133000;
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}
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}
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static int sc520_freq_target(struct cpufreq_policy *policy, unsigned int state)
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{
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u8 clockspeed_reg;
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local_irq_disable();
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clockspeed_reg = *cpuctl & ~0x03;
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*cpuctl = clockspeed_reg | sc520_freq_table[state].driver_data;
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local_irq_enable();
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return 0;
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}
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/*
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* Module init and exit code
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*/
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static int sc520_freq_cpu_init(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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/* capability check */
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if (c->x86_vendor != X86_VENDOR_AMD ||
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c->x86 != 4 || c->x86_model != 9)
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return -ENODEV;
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/* cpuinfo and default policy values */
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policy->cpuinfo.transition_latency = 1000000; /* 1ms */
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return cpufreq_table_validate_and_show(policy, sc520_freq_table);
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}
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static struct cpufreq_driver sc520_freq_driver = {
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.get = sc520_freq_get_cpu_frequency,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = sc520_freq_target,
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.init = sc520_freq_cpu_init,
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.name = "sc520_freq",
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.attr = cpufreq_generic_attr,
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};
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static const struct x86_cpu_id sc520_ids[] = {
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{ X86_VENDOR_AMD, 4, 9 },
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, sc520_ids);
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static int __init sc520_freq_init(void)
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{
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int err;
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if (!x86_match_cpu(sc520_ids))
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return -ENODEV;
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cpuctl = ioremap((unsigned long)(MMCR_BASE + OFFS_CPUCTL), 1);
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if (!cpuctl) {
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printk(KERN_ERR "sc520_freq: error: failed to remap memory\n");
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return -ENOMEM;
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}
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err = cpufreq_register_driver(&sc520_freq_driver);
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if (err)
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iounmap(cpuctl);
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return err;
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}
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static void __exit sc520_freq_exit(void)
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{
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cpufreq_unregister_driver(&sc520_freq_driver);
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iounmap(cpuctl);
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}
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Sean Young <sean@mess.org>");
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MODULE_DESCRIPTION("cpufreq driver for AMD's Elan sc520 CPU");
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module_init(sc520_freq_init);
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module_exit(sc520_freq_exit);
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