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00a9730e10
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
26 lines
883 B
C
26 lines
883 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_TLBFLUSH_H
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#define __ASM_TLBFLUSH_H
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/*
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* TLB flushing:
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*
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* - flush_tlb_all() flushes all processes TLB entries
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* - flush_tlb_mm(mm) flushes the specified mm context TLB entries
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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*/
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extern void flush_tlb_all(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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extern void flush_tlb_one(unsigned long vaddr);
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#endif
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