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https://github.com/edk2-porting/linux-next.git
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b633648c5a
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
132 lines
3.0 KiB
C
132 lines
3.0 KiB
C
/*
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* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
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*
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* This file define the irq handler for MSP PER subsystem interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include <asm/mipsregs.h>
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#include <msp_cic_int.h>
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#include <msp_regs.h>
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/*
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* Convenience Macro. Should be somewhere generic.
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*/
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#define get_current_vpe() \
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((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
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#ifdef CONFIG_SMP
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/*
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* The PER registers must be protected from concurrent access.
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*/
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static DEFINE_SPINLOCK(per_lock);
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#endif
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/* ensure writes to per are completed */
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static inline void per_wmb(void)
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{
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const volatile void __iomem *per_mem = PER_INT_MSK_REG;
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volatile u32 dummy_read;
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wmb();
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dummy_read = __raw_readl(per_mem);
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dummy_read++;
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}
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static inline void unmask_per_irq(struct irq_data *d)
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{
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#ifdef CONFIG_SMP
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unsigned long flags;
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spin_lock_irqsave(&per_lock, flags);
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*PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE));
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spin_unlock_irqrestore(&per_lock, flags);
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#else
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*PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE));
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#endif
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per_wmb();
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}
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static inline void mask_per_irq(struct irq_data *d)
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{
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#ifdef CONFIG_SMP
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unsigned long flags;
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spin_lock_irqsave(&per_lock, flags);
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*PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE));
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spin_unlock_irqrestore(&per_lock, flags);
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#else
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*PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE));
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#endif
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per_wmb();
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}
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static inline void msp_per_irq_ack(struct irq_data *d)
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{
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mask_per_irq(d);
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/*
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* In the PER interrupt controller, only bits 11 and 10
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* are write-to-clear, (SPI TX complete, SPI RX complete).
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* It does nothing for any others.
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*/
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*PER_INT_STS_REG = (1 << (d->irq - MSP_PER_INTBASE));
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}
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#ifdef CONFIG_SMP
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static int msp_per_irq_set_affinity(struct irq_data *d,
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const struct cpumask *affinity, bool force)
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{
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/* WTF is this doing ????? */
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unmask_per_irq(d);
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return 0;
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}
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#endif
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static struct irq_chip msp_per_irq_controller = {
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.name = "MSP_PER",
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.irq_enable = unmask_per_irq,
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.irq_disable = mask_per_irq,
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.irq_ack = msp_per_irq_ack,
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#ifdef CONFIG_SMP
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.irq_set_affinity = msp_per_irq_set_affinity,
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#endif
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};
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void __init msp_per_irq_init(void)
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{
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int i;
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/* Mask/clear interrupts. */
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*PER_INT_MSK_REG = 0x00000000;
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*PER_INT_STS_REG = 0xFFFFFFFF;
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/* initialize all the IRQ descriptors */
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for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
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irq_set_chip(i, &msp_per_irq_controller);
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}
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}
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void msp_per_irq_dispatch(void)
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{
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u32 per_mask = *PER_INT_MSK_REG;
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u32 per_status = *PER_INT_STS_REG;
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u32 pending;
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pending = per_status & per_mask;
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if (pending) {
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do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1);
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} else {
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spurious_interrupt();
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}
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}
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