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b60b61d412
When adding CPU to the SMP group and enabling the coherency on this CPU we must protect the register access. The previous implementation claims to be atomic but doesn't provide any protection against parallel access to the coherency fabric control and configuration registers. This patch fixes this by using the ldrex and strex mechanism. This method should be used in all accesses to those registers. [gregory.clement@free-electrons.com: fixed the commit's topic] Signed-off-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
56 lines
1.3 KiB
ArmAsm
56 lines
1.3 KiB
ArmAsm
/*
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* Coherency fabric: low level functions
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file implements the assembly function to add a CPU to the
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* coherency fabric. This function is called by each of the secondary
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* CPUs during their early boot in an SMP kernel, this why this
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* function have to callable from assembly. It can also be called by a
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* primary CPU from C code during its boot.
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*/
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#include <linux/linkage.h>
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#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
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#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
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.text
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/*
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* r0: Coherency fabric base register address
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* r1: HW CPU id
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*/
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ENTRY(ll_set_cpu_coherent)
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/* Create bit by cpu index */
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mov r3, #(1 << 24)
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lsl r1, r3, r1
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/* Add CPU to SMP group - Atomic */
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add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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ldrex r2, [r3]
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orr r2, r2, r1
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strex r0, r2, [r3]
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cmp r0, #0
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bne 1b
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/* Enable coherency on CPU - Atomic */
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add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
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1:
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ldrex r2, [r3]
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orr r2, r2, r1
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strex r0, r2, [r3]
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cmp r0, #0
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bne 1b
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dsb
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mov r0, #0
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mov pc, lr
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ENDPROC(ll_set_cpu_coherent)
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