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d7b16e75d4
Check for watchdog_ops structures that are only stored in the ops field of
a watchdog_device structure. This field is declared const, so watchdog_ops
structures that have this property can be declared as const also.
This issue was detected using Coccinelle and the following semantic patch:
@r
disable optional_qualifier@
identifier i;
position p;
@@
static struct watchdog_ops i@p = { ... };
@ok@
identifier r.i;
struct watchdog_device e;
position p;
@@
e.ops = &i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct watchdog_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct watchdog_ops i = { ... };
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
254 lines
6.2 KiB
C
254 lines
6.2 KiB
C
/*
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* Driver for STM32 Independent Watchdog
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*
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* Copyright (C) Yannick Fertre 2017
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* Author: Yannick Fertre <yannick.fertre@st.com>
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*
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* This driver is based on tegra_wdt.c
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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/* IWDG registers */
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#define IWDG_KR 0x00 /* Key register */
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#define IWDG_PR 0x04 /* Prescaler Register */
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#define IWDG_RLR 0x08 /* ReLoad Register */
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#define IWDG_SR 0x0C /* Status Register */
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#define IWDG_WINR 0x10 /* Windows Register */
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/* IWDG_KR register bit mask */
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#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
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#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
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#define KR_KEY_EWA 0x5555 /* write access enable */
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#define KR_KEY_DWA 0x0000 /* write access disable */
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/* IWDG_PR register bit values */
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#define PR_4 0x00 /* prescaler set to 4 */
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#define PR_8 0x01 /* prescaler set to 8 */
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#define PR_16 0x02 /* prescaler set to 16 */
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#define PR_32 0x03 /* prescaler set to 32 */
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#define PR_64 0x04 /* prescaler set to 64 */
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#define PR_128 0x05 /* prescaler set to 128 */
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#define PR_256 0x06 /* prescaler set to 256 */
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/* IWDG_RLR register values */
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#define RLR_MIN 0x07C /* min value supported by reload register */
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#define RLR_MAX 0xFFF /* max value supported by reload register */
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/* IWDG_SR register bit mask */
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#define FLAG_PVU BIT(0) /* Watchdog prescaler value update */
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#define FLAG_RVU BIT(1) /* Watchdog counter reload value update */
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/* set timeout to 100000 us */
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#define TIMEOUT_US 100000
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#define SLEEP_US 1000
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struct stm32_iwdg {
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struct watchdog_device wdd;
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void __iomem *regs;
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struct clk *clk;
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unsigned int rate;
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};
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static inline u32 reg_read(void __iomem *base, u32 reg)
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{
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return readl_relaxed(base + reg);
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}
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static inline void reg_write(void __iomem *base, u32 reg, u32 val)
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{
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writel_relaxed(val, base + reg);
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}
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static int stm32_iwdg_start(struct watchdog_device *wdd)
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{
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struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
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u32 val = FLAG_PVU | FLAG_RVU;
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u32 reload;
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int ret;
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dev_dbg(wdd->parent, "%s\n", __func__);
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/* prescaler fixed to 256 */
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reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1,
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RLR_MIN, RLR_MAX);
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/* enable write access */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
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/* set prescaler & reload registers */
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reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
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reg_write(wdt->regs, IWDG_RLR, reload);
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reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
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/* wait for the registers to be updated (max 100ms) */
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ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
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!(val & (FLAG_PVU | FLAG_RVU)),
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SLEEP_US, TIMEOUT_US);
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if (ret) {
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dev_err(wdd->parent,
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"Fail to set prescaler or reload registers\n");
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return ret;
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}
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/* reload watchdog */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
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return 0;
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}
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static int stm32_iwdg_ping(struct watchdog_device *wdd)
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{
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struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
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dev_dbg(wdd->parent, "%s\n", __func__);
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/* reload watchdog */
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reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
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return 0;
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}
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static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
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wdd->timeout = timeout;
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if (watchdog_active(wdd))
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return stm32_iwdg_start(wdd);
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return 0;
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}
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static const struct watchdog_info stm32_iwdg_info = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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.identity = "STM32 Independent Watchdog",
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};
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static const struct watchdog_ops stm32_iwdg_ops = {
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.owner = THIS_MODULE,
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.start = stm32_iwdg_start,
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.ping = stm32_iwdg_ping,
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.set_timeout = stm32_iwdg_set_timeout,
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};
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static int stm32_iwdg_probe(struct platform_device *pdev)
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{
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struct watchdog_device *wdd;
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struct stm32_iwdg *wdt;
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struct resource *res;
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void __iomem *regs;
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struct clk *clk;
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int ret;
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/* This is the timer base. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(regs)) {
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dev_err(&pdev->dev, "Could not get resource\n");
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return PTR_ERR(regs);
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}
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Unable to get clock\n");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk);
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return ret;
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}
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/*
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* Allocate our watchdog driver data, which has the
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* struct watchdog_device nested within it.
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*/
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt) {
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ret = -ENOMEM;
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goto err;
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}
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/* Initialize struct stm32_iwdg. */
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wdt->regs = regs;
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wdt->clk = clk;
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wdt->rate = clk_get_rate(clk);
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/* Initialize struct watchdog_device. */
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wdd = &wdt->wdd;
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wdd->info = &stm32_iwdg_info;
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wdd->ops = &stm32_iwdg_ops;
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wdd->min_timeout = ((RLR_MIN + 1) * 256) / wdt->rate;
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wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 256 * 1000) / wdt->rate;
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wdd->parent = &pdev->dev;
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watchdog_set_drvdata(wdd, wdt);
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watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
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ret = watchdog_init_timeout(wdd, 0, &pdev->dev);
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if (ret)
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dev_warn(&pdev->dev,
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"unable to set timeout value, using default\n");
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ret = watchdog_register_device(wdd);
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if (ret) {
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dev_err(&pdev->dev, "failed to register watchdog device\n");
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goto err;
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}
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platform_set_drvdata(pdev, wdt);
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return 0;
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err:
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clk_disable_unprepare(clk);
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return ret;
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}
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static int stm32_iwdg_remove(struct platform_device *pdev)
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{
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struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&wdt->wdd);
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clk_disable_unprepare(wdt->clk);
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return 0;
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}
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static const struct of_device_id stm32_iwdg_of_match[] = {
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{ .compatible = "st,stm32-iwdg" },
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{ /* end node */ }
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};
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MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
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static struct platform_driver stm32_iwdg_driver = {
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.probe = stm32_iwdg_probe,
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.remove = stm32_iwdg_remove,
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.driver = {
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.name = "iwdg",
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.of_match_table = stm32_iwdg_of_match,
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},
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};
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module_platform_driver(stm32_iwdg_driver);
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MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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