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f54d186700
I plan to usurp the short name of struct fence for a core kernel struct, and so I need to rename the specialised fence/timeline for DMA operations to make room. A consensus was reached in https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html that making clear this fence applies to DMA operations was a good thing. Since then the patch has grown a bit as usage increases, so hopefully it remains a good thing! (v2...: rebase, rerun spatch) v3: Compile on msm, spotted a manual fixup that I broke. v4: Try again for msm, sorry Daniel coccinelle script: @@ @@ - struct fence + struct dma_fence @@ @@ - struct fence_ops + struct dma_fence_ops @@ @@ - struct fence_cb + struct dma_fence_cb @@ @@ - struct fence_array + struct dma_fence_array @@ @@ - enum fence_flag_bits + enum dma_fence_flag_bits @@ @@ ( - fence_init + dma_fence_init | - fence_release + dma_fence_release | - fence_free + dma_fence_free | - fence_get + dma_fence_get | - fence_get_rcu + dma_fence_get_rcu | - fence_put + dma_fence_put | - fence_signal + dma_fence_signal | - fence_signal_locked + dma_fence_signal_locked | - fence_default_wait + dma_fence_default_wait | - fence_add_callback + dma_fence_add_callback | - fence_remove_callback + dma_fence_remove_callback | - fence_enable_sw_signaling + dma_fence_enable_sw_signaling | - fence_is_signaled_locked + dma_fence_is_signaled_locked | - fence_is_signaled + dma_fence_is_signaled | - fence_is_later + dma_fence_is_later | - fence_later + dma_fence_later | - fence_wait_timeout + dma_fence_wait_timeout | - fence_wait_any_timeout + dma_fence_wait_any_timeout | - fence_wait + dma_fence_wait | - fence_context_alloc + dma_fence_context_alloc | - fence_array_create + dma_fence_array_create | - to_fence_array + to_dma_fence_array | - fence_is_array + dma_fence_is_array | - trace_fence_emit + trace_dma_fence_emit | - FENCE_TRACE + DMA_FENCE_TRACE | - FENCE_WARN + DMA_FENCE_WARN | - FENCE_ERR + DMA_FENCE_ERR ) ( ... ) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161025120045.28839-1-chris@chris-wilson.co.uk
225 lines
5.6 KiB
C
225 lines
5.6 KiB
C
/*
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* Copyright (C) 2015 Etnaviv Project
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ETNAVIV_GPU_H__
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#define __ETNAVIV_GPU_H__
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "etnaviv_drv.h"
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struct etnaviv_gem_submit;
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struct etnaviv_vram_mapping;
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struct etnaviv_chip_identity {
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/* Chip model. */
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u32 model;
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/* Revision value.*/
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u32 revision;
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/* Supported feature fields. */
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u32 features;
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/* Supported minor feature fields. */
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u32 minor_features0;
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/* Supported minor feature 1 fields. */
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u32 minor_features1;
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/* Supported minor feature 2 fields. */
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u32 minor_features2;
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/* Supported minor feature 3 fields. */
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u32 minor_features3;
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/* Supported minor feature 4 fields. */
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u32 minor_features4;
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/* Supported minor feature 5 fields. */
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u32 minor_features5;
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/* Number of streams supported. */
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u32 stream_count;
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/* Total number of temporary registers per thread. */
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u32 register_max;
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/* Maximum number of threads. */
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u32 thread_count;
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/* Number of shader cores. */
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u32 shader_core_count;
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/* Size of the vertex cache. */
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u32 vertex_cache_size;
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/* Number of entries in the vertex output buffer. */
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u32 vertex_output_buffer_size;
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/* Number of pixel pipes. */
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u32 pixel_pipes;
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/* Number of instructions. */
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u32 instruction_count;
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/* Number of constants. */
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u32 num_constants;
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/* Buffer size */
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u32 buffer_size;
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/* Number of varyings */
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u8 varyings_count;
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};
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struct etnaviv_event {
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bool used;
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struct dma_fence *fence;
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};
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struct etnaviv_cmdbuf;
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struct etnaviv_gpu {
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struct drm_device *drm;
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struct device *dev;
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struct mutex lock;
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struct etnaviv_chip_identity identity;
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struct etnaviv_file_private *lastctx;
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bool switch_context;
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/* 'ring'-buffer: */
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struct etnaviv_cmdbuf *buffer;
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int exec_state;
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/* bus base address of memory */
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u32 memory_base;
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/* event management: */
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struct etnaviv_event event[30];
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struct completion event_free;
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spinlock_t event_spinlock;
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/* list of currently in-flight command buffers */
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struct list_head active_cmd_list;
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u32 idle_mask;
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/* Fencing support */
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u32 next_fence;
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u32 active_fence;
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u32 completed_fence;
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u32 retired_fence;
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wait_queue_head_t fence_event;
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u64 fence_context;
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spinlock_t fence_spinlock;
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/* worker for handling active-list retiring: */
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struct work_struct retire_work;
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void __iomem *mmio;
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int irq;
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struct etnaviv_iommu *mmu;
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/* Power Control: */
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struct clk *clk_bus;
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struct clk *clk_core;
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struct clk *clk_shader;
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/* Hang Detction: */
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#define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
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#define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
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struct timer_list hangcheck_timer;
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u32 hangcheck_fence;
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u32 hangcheck_dma_addr;
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struct work_struct recover_work;
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};
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struct etnaviv_cmdbuf {
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/* device this cmdbuf is allocated for */
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struct etnaviv_gpu *gpu;
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/* user context key, must be unique between all active users */
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struct etnaviv_file_private *ctx;
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/* cmdbuf properties */
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void *vaddr;
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dma_addr_t paddr;
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u32 size;
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u32 user_size;
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/* vram node used if the cmdbuf is mapped through the MMUv2 */
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struct drm_mm_node vram_node;
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/* fence after which this buffer is to be disposed */
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struct dma_fence *fence;
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/* target exec state */
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u32 exec_state;
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/* per GPU in-flight list */
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struct list_head node;
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/* BOs attached to this command buffer */
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unsigned int nr_bos;
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struct etnaviv_vram_mapping *bo_map[0];
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};
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static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
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{
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etnaviv_writel(data, gpu->mmio + reg);
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}
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static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
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{
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return etnaviv_readl(gpu->mmio + reg);
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}
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static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
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{
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return fence_after_eq(gpu->completed_fence, fence);
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}
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static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
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{
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return fence_after_eq(gpu->retired_fence, fence);
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}
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int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
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int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
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#ifdef CONFIG_DEBUG_FS
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int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
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#endif
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int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
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unsigned int context, bool exclusive);
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void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
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int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
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u32 fence, struct timespec *timeout);
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int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
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struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
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int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
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struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf);
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struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu,
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u32 size, size_t nr_bos);
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void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf);
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int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
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void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
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int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
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void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
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extern struct platform_driver etnaviv_gpu_driver;
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#endif /* __ETNAVIV_GPU_H__ */
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