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https://github.com/edk2-porting/linux-next.git
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2b46cd23a5
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
184 lines
5.4 KiB
C
184 lines
5.4 KiB
C
/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
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#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
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#define MMSS_AHB_CLK_SRC 0
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#define MMSS_AXI_CLK_SRC 1
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#define MMPLL0 2
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#define MMPLL0_VOTE 3
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#define MMPLL1 4
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#define MMPLL1_VOTE 5
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#define MMPLL2 6
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#define MMPLL3 7
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#define MMPLL4 8
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#define CSI0_CLK_SRC 9
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#define CSI1_CLK_SRC 10
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#define CSI2_CLK_SRC 11
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#define CSI3_CLK_SRC 12
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#define VCODEC0_CLK_SRC 13
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#define VFE0_CLK_SRC 14
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#define VFE1_CLK_SRC 15
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#define MDP_CLK_SRC 16
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#define PCLK0_CLK_SRC 17
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#define PCLK1_CLK_SRC 18
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#define OCMEMNOC_CLK_SRC 19
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#define GFX3D_CLK_SRC 20
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#define JPEG0_CLK_SRC 21
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#define JPEG1_CLK_SRC 22
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#define JPEG2_CLK_SRC 23
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#define EDPPIXEL_CLK_SRC 24
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#define EXTPCLK_CLK_SRC 25
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#define VP_CLK_SRC 26
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#define CCI_CLK_SRC 27
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#define CAMSS_GP0_CLK_SRC 28
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#define CAMSS_GP1_CLK_SRC 29
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#define MCLK0_CLK_SRC 30
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#define MCLK1_CLK_SRC 31
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#define MCLK2_CLK_SRC 32
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#define MCLK3_CLK_SRC 33
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#define CSI0PHYTIMER_CLK_SRC 34
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#define CSI1PHYTIMER_CLK_SRC 35
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#define CSI2PHYTIMER_CLK_SRC 36
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#define CPP_CLK_SRC 37
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#define BYTE0_CLK_SRC 38
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#define BYTE1_CLK_SRC 39
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#define EDPAUX_CLK_SRC 40
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#define EDPLINK_CLK_SRC 41
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#define ESC0_CLK_SRC 42
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#define ESC1_CLK_SRC 43
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#define HDMI_CLK_SRC 44
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#define VSYNC_CLK_SRC 45
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#define RBCPR_CLK_SRC 46
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#define RBBMTIMER_CLK_SRC 47
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#define MAPLE_CLK_SRC 48
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#define VDP_CLK_SRC 49
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#define VPU_BUS_CLK_SRC 50
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#define MMSS_CXO_CLK 51
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#define MMSS_SLEEPCLK_CLK 52
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#define AVSYNC_AHB_CLK 53
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#define AVSYNC_EDPPIXEL_CLK 54
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#define AVSYNC_EXTPCLK_CLK 55
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#define AVSYNC_PCLK0_CLK 56
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#define AVSYNC_PCLK1_CLK 57
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#define AVSYNC_VP_CLK 58
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#define CAMSS_AHB_CLK 59
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#define CAMSS_CCI_CCI_AHB_CLK 60
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#define CAMSS_CCI_CCI_CLK 61
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#define CAMSS_CSI0_AHB_CLK 62
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#define CAMSS_CSI0_CLK 63
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#define CAMSS_CSI0PHY_CLK 64
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#define CAMSS_CSI0PIX_CLK 65
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#define CAMSS_CSI0RDI_CLK 66
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#define CAMSS_CSI1_AHB_CLK 67
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#define CAMSS_CSI1_CLK 68
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#define CAMSS_CSI1PHY_CLK 69
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#define CAMSS_CSI1PIX_CLK 70
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#define CAMSS_CSI1RDI_CLK 71
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#define CAMSS_CSI2_AHB_CLK 72
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#define CAMSS_CSI2_CLK 73
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#define CAMSS_CSI2PHY_CLK 74
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#define CAMSS_CSI2PIX_CLK 75
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#define CAMSS_CSI2RDI_CLK 76
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#define CAMSS_CSI3_AHB_CLK 77
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#define CAMSS_CSI3_CLK 78
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#define CAMSS_CSI3PHY_CLK 79
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#define CAMSS_CSI3PIX_CLK 80
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#define CAMSS_CSI3RDI_CLK 81
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#define CAMSS_CSI_VFE0_CLK 82
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#define CAMSS_CSI_VFE1_CLK 83
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#define CAMSS_GP0_CLK 84
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#define CAMSS_GP1_CLK 85
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#define CAMSS_ISPIF_AHB_CLK 86
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#define CAMSS_JPEG_JPEG0_CLK 87
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#define CAMSS_JPEG_JPEG1_CLK 88
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#define CAMSS_JPEG_JPEG2_CLK 89
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#define CAMSS_JPEG_JPEG_AHB_CLK 90
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#define CAMSS_JPEG_JPEG_AXI_CLK 91
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#define CAMSS_MCLK0_CLK 92
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#define CAMSS_MCLK1_CLK 93
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#define CAMSS_MCLK2_CLK 94
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#define CAMSS_MCLK3_CLK 95
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#define CAMSS_MICRO_AHB_CLK 96
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#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
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#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
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#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
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#define CAMSS_TOP_AHB_CLK 100
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#define CAMSS_VFE_CPP_AHB_CLK 101
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#define CAMSS_VFE_CPP_CLK 102
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#define CAMSS_VFE_VFE0_CLK 103
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#define CAMSS_VFE_VFE1_CLK 104
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#define CAMSS_VFE_VFE_AHB_CLK 105
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#define CAMSS_VFE_VFE_AXI_CLK 106
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#define MDSS_AHB_CLK 107
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#define MDSS_AXI_CLK 108
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#define MDSS_BYTE0_CLK 109
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#define MDSS_BYTE1_CLK 110
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#define MDSS_EDPAUX_CLK 111
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#define MDSS_EDPLINK_CLK 112
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#define MDSS_EDPPIXEL_CLK 113
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#define MDSS_ESC0_CLK 114
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#define MDSS_ESC1_CLK 115
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#define MDSS_EXTPCLK_CLK 116
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#define MDSS_HDMI_AHB_CLK 117
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#define MDSS_HDMI_CLK 118
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#define MDSS_MDP_CLK 119
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#define MDSS_MDP_LUT_CLK 120
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#define MDSS_PCLK0_CLK 121
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#define MDSS_PCLK1_CLK 122
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#define MDSS_VSYNC_CLK 123
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#define MMSS_RBCPR_AHB_CLK 124
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#define MMSS_RBCPR_CLK 125
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#define MMSS_SPDM_AHB_CLK 126
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#define MMSS_SPDM_AXI_CLK 127
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#define MMSS_SPDM_CSI0_CLK 128
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#define MMSS_SPDM_GFX3D_CLK 129
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#define MMSS_SPDM_JPEG0_CLK 130
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#define MMSS_SPDM_JPEG1_CLK 131
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#define MMSS_SPDM_JPEG2_CLK 132
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#define MMSS_SPDM_MDP_CLK 133
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#define MMSS_SPDM_PCLK0_CLK 134
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#define MMSS_SPDM_PCLK1_CLK 135
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#define MMSS_SPDM_VCODEC0_CLK 136
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#define MMSS_SPDM_VFE0_CLK 137
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#define MMSS_SPDM_VFE1_CLK 138
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#define MMSS_SPDM_RM_AXI_CLK 139
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#define MMSS_SPDM_RM_OCMEMNOC_CLK 140
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#define MMSS_MISC_AHB_CLK 141
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#define MMSS_MMSSNOC_AHB_CLK 142
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#define MMSS_MMSSNOC_BTO_AHB_CLK 143
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#define MMSS_MMSSNOC_AXI_CLK 144
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#define MMSS_S0_AXI_CLK 145
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#define OCMEMCX_AHB_CLK 146
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#define OCMEMCX_OCMEMNOC_CLK 147
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#define OXILI_OCMEMGX_CLK 148
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#define OXILI_GFX3D_CLK 149
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#define OXILI_RBBMTIMER_CLK 150
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#define OXILICX_AHB_CLK 151
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#define VENUS0_AHB_CLK 152
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#define VENUS0_AXI_CLK 153
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#define VENUS0_CORE0_VCODEC_CLK 154
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#define VENUS0_CORE1_VCODEC_CLK 155
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#define VENUS0_OCMEMNOC_CLK 156
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#define VENUS0_VCODEC0_CLK 157
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#define VPU_AHB_CLK 158
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#define VPU_AXI_CLK 159
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#define VPU_BUS_CLK 160
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#define VPU_CXO_CLK 161
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#define VPU_MAPLE_CLK 162
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#define VPU_SLEEP_CLK 163
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#define VPU_VDP_CLK 164
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#endif
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