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ccac71a7f0
Both OMAP4 and 5 exhibit the same revision ID in the REVISION register but they have different number of ports i.e. 2 and 3 respectively. So we can't rely on REVISION register for number of ports on OMAP5 and depend on platform data (or device tree) instead. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/*
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* usb-omap.h - Platform data for the various OMAP USB IPs
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
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*
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* This software is distributed under the terms of the GNU General Public
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* License ("GPL") version 2, as published by the Free Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define OMAP3_HS_USB_PORTS 3
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enum usbhs_omap_port_mode {
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OMAP_USBHS_PORT_MODE_UNUSED,
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OMAP_EHCI_PORT_MODE_PHY,
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OMAP_EHCI_PORT_MODE_TLL,
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OMAP_EHCI_PORT_MODE_HSIC,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
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};
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struct usbtll_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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};
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struct ehci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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unsigned phy_reset:1;
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};
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struct ohci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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unsigned es2_compatibility:1;
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};
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struct usbhs_omap_platform_data {
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int nports;
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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struct ehci_hcd_omap_platform_data *ehci_data;
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struct ohci_hcd_omap_platform_data *ohci_data;
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/* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
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unsigned single_ulpi_bypass:1;
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unsigned es2_compatibility:1;
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unsigned phy_reset:1;
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};
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/*-------------------------------------------------------------------------*/
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struct omap_musb_board_data {
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u8 interface_type;
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u8 mode;
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u16 power;
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unsigned extvbus:1;
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void (*set_phy_power)(u8 on);
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void (*clear_irq)(void);
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void (*set_mode)(u8 mode);
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void (*reset)(void);
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};
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enum musb_interface {
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MUSB_INTERFACE_ULPI,
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MUSB_INTERFACE_UTMI
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};
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