mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
c987d12f84
and use max_pfn directly. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
173 lines
4.4 KiB
C
173 lines
4.4 KiB
C
/* Various workarounds for chipset bugs.
|
|
This code runs very early and can't use the regular PCI subsystem
|
|
The entries are keyed to PCI bridges which usually identify chipsets
|
|
uniquely.
|
|
This is only for whole classes of chipsets with specific problems which
|
|
need early invasive action (e.g. before the timers are initialized).
|
|
Most PCI device specific workarounds can be done later and should be
|
|
in standard PCI quirks
|
|
Mainboard specific bugs should be handled by DMI entries.
|
|
CPU specific bugs in setup.c */
|
|
|
|
#include <linux/pci.h>
|
|
#include <linux/acpi.h>
|
|
#include <linux/pci_ids.h>
|
|
#include <asm/pci-direct.h>
|
|
#include <asm/dma.h>
|
|
#include <asm/io_apic.h>
|
|
#include <asm/apic.h>
|
|
|
|
#ifdef CONFIG_GART_IOMMU
|
|
#include <asm/gart.h>
|
|
#endif
|
|
|
|
static void __init fix_hypertransport_config(int num, int slot, int func)
|
|
{
|
|
u32 htcfg;
|
|
/*
|
|
* we found a hypertransport bus
|
|
* make sure that we are broadcasting
|
|
* interrupts to all cpus on the ht bus
|
|
* if we're using extended apic ids
|
|
*/
|
|
htcfg = read_pci_config(num, slot, func, 0x68);
|
|
if (htcfg & (1 << 18)) {
|
|
printk(KERN_INFO "Detected use of extended apic ids "
|
|
"on hypertransport bus\n");
|
|
if ((htcfg & (1 << 17)) == 0) {
|
|
printk(KERN_INFO "Enabling hypertransport extended "
|
|
"apic interrupt broadcast\n");
|
|
printk(KERN_INFO "Note this is a bios bug, "
|
|
"please contact your hw vendor\n");
|
|
htcfg |= (1 << 17);
|
|
write_pci_config(num, slot, func, 0x68, htcfg);
|
|
}
|
|
}
|
|
|
|
|
|
}
|
|
|
|
static void __init via_bugs(int num, int slot, int func)
|
|
{
|
|
#ifdef CONFIG_GART_IOMMU
|
|
if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
|
|
!gart_iommu_aperture_allowed) {
|
|
printk(KERN_INFO
|
|
"Looks like a VIA chipset. Disabling IOMMU."
|
|
" Override with iommu=allowed\n");
|
|
gart_iommu_aperture_disabled = 1;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_ACPI
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
|
|
static int __init nvidia_hpet_check(struct acpi_table_header *header)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_X86_IO_APIC */
|
|
#endif /* CONFIG_ACPI */
|
|
|
|
static void __init nvidia_bugs(int num, int slot, int func)
|
|
{
|
|
#ifdef CONFIG_ACPI
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
/*
|
|
* All timer overrides on Nvidia are
|
|
* wrong unless HPET is enabled.
|
|
* Unfortunately that's not true on many Asus boards.
|
|
* We don't know yet how to detect this automatically, but
|
|
* at least allow a command line override.
|
|
*/
|
|
if (acpi_use_timer_override)
|
|
return;
|
|
|
|
if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
|
|
acpi_skip_timer_override = 1;
|
|
printk(KERN_INFO "Nvidia board "
|
|
"detected. Ignoring ACPI "
|
|
"timer override.\n");
|
|
printk(KERN_INFO "If you got timer trouble "
|
|
"try acpi_use_timer_override\n");
|
|
}
|
|
#endif
|
|
#endif
|
|
/* RED-PEN skip them on mptables too? */
|
|
|
|
}
|
|
|
|
#define QFLAG_APPLY_ONCE 0x1
|
|
#define QFLAG_APPLIED 0x2
|
|
#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
|
|
struct chipset {
|
|
u32 vendor;
|
|
u32 device;
|
|
u32 class;
|
|
u32 class_mask;
|
|
u32 flags;
|
|
void (*f)(int num, int slot, int func);
|
|
};
|
|
|
|
static struct chipset early_qrk[] __initdata = {
|
|
{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
|
|
{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
|
|
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
|
|
{}
|
|
};
|
|
|
|
static void __init check_dev_quirk(int num, int slot, int func)
|
|
{
|
|
u16 class;
|
|
u16 vendor;
|
|
u16 device;
|
|
u8 type;
|
|
int i;
|
|
|
|
class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
|
|
|
|
if (class == 0xffff)
|
|
return;
|
|
|
|
vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
|
|
|
|
device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
|
|
|
|
for (i = 0; early_qrk[i].f != NULL; i++) {
|
|
if (((early_qrk[i].vendor == PCI_ANY_ID) ||
|
|
(early_qrk[i].vendor == vendor)) &&
|
|
((early_qrk[i].device == PCI_ANY_ID) ||
|
|
(early_qrk[i].device == device)) &&
|
|
(!((early_qrk[i].class ^ class) &
|
|
early_qrk[i].class_mask))) {
|
|
if ((early_qrk[i].flags &
|
|
QFLAG_DONE) != QFLAG_DONE)
|
|
early_qrk[i].f(num, slot, func);
|
|
early_qrk[i].flags |= QFLAG_APPLIED;
|
|
}
|
|
}
|
|
|
|
type = read_pci_config_byte(num, slot, func,
|
|
PCI_HEADER_TYPE);
|
|
if (!(type & 0x80))
|
|
return;
|
|
}
|
|
|
|
void __init early_quirks(void)
|
|
{
|
|
int num, slot, func;
|
|
|
|
if (!early_pci_allowed())
|
|
return;
|
|
|
|
/* Poor man's PCI discovery */
|
|
for (num = 0; num < 32; num++)
|
|
for (slot = 0; slot < 32; slot++)
|
|
for (func = 0; func < 8; func++)
|
|
check_dev_quirk(num, slot, func);
|
|
}
|