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af8b128719
As per feature-removal-schedule.txt. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Acked-by: Alan Cox <alan@redhat.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
219 lines
7.0 KiB
C
219 lines
7.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_SERIAL_H
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#define _ASM_SERIAL_H
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/*
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* This assumes you have a 1.8432 MHz clock for your UART.
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*
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* It'd be nice if someone built a serial card with a 24.576 MHz
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* clock, since the 16550A is capable of handling a top speed of 1.5
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* megabits/second; but this requires the faster clock.
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*/
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#define BASE_BAUD (1843200 / 16)
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/* Standard COM flags (except for COM4, because of the 8514 problem) */
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
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#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
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#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
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#endif
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#ifdef CONFIG_MACH_JAZZ
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#include <asm/jazz.h>
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#ifndef CONFIG_OLIVETTI_M700
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/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
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exactly which ones ... XXX */
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#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
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#else
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/* but the M700 isn't such a strange beast */
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#define JAZZ_BASE_BAUD BASE_BAUD
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#endif
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#define _JAZZ_SERIAL_INIT(int, base) \
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{ .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
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.io_type = SERIAL_IO_MEM }
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#define JAZZ_SERIAL_PORT_DEFNS \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
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#else
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#define JAZZ_SERIAL_PORT_DEFNS
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#endif
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/*
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* Galileo EV64120 evaluation board
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*/
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#ifdef CONFIG_MIPS_EV64120
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#include <mach-gt64120.h>
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#define EV64120_SERIAL_PORT_DEFNS \
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{ .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }, \
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{ .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM },
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#else
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#define EV64120_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
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#define STD_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
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{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
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{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
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{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
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#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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#define STD_SERIAL_PORT_DEFNS
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#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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#ifdef CONFIG_MOMENCO_JAGUAR_ATX
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define JAGUAR_ATX_UART_CLK 20000000
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#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
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#define JAGUAR_ATX_SERIAL1_IRQ 6
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#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
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#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
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{ .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
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.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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.iomem_base = (u8 *) base, iomem_reg_shift: 2, \
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io_type: SERIAL_IO_MEM }
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#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
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_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
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#else
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#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MOMENCO_OCELOT_3
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#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_3_SERIAL_IRQ 6
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#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
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#define _OCELOT_3_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, iomem_reg_shift: 2, \
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io_type: SERIAL_IO_MEM }
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#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
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_OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
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#else
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#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MOMENCO_OCELOT
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define OCELOT_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_SERIAL1_IRQ 4
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#define OCELOT_SERIAL1_BASE 0xe0001020
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#define _OCELOT_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }
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#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
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_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
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#else
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#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MOMENCO_OCELOT_G
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_G_SERIAL1_IRQ 4
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#if 0
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#define OCELOT_G_SERIAL1_BASE 0xe0001020
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#else
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#define OCELOT_G_SERIAL1_BASE 0xfd000020
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#endif
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#define _OCELOT_G_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
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.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }
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#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
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_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
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#else
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#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_MOMENCO_OCELOT_C
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_C_SERIAL1_IRQ 80
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#define OCELOT_C_SERIAL1_BASE 0xfd000020
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#define OCELOT_C_SERIAL2_IRQ 81
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#define OCELOT_C_SERIAL2_BASE 0xfd000000
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#define _OCELOT_C_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_C_BASE_BAUD, \
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.irq = (int), \
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.flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, \
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.iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM \
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}
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#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
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_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
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_OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
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#else
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#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_DDB5477
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#include <asm/ddb5xxx/ddb5477.h>
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#define DDB5477_SERIAL_PORT_DEFNS \
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{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
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.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
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.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
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{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
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.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
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.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
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#else
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#define DDB5477_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_SGI_IP32
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/*
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* The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
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* They are initialized in ip32_setup
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*/
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#define IP32_SERIAL_PORT_DEFNS \
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{},{},
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#else
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#define IP32_SERIAL_PORT_DEFNS
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#endif /* CONFIG_SGI_IP32 */
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#define SERIAL_PORT_DFNS \
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DDB5477_SERIAL_PORT_DEFNS \
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EV64120_SERIAL_PORT_DEFNS \
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IP32_SERIAL_PORT_DEFNS \
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JAZZ_SERIAL_PORT_DEFNS \
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STD_SERIAL_PORT_DEFNS \
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MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
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MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
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MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
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MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
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#endif /* _ASM_SERIAL_H */
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