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linux-next/arch/x86/power
Andy Lutomirski f34902c5c6 x86/hibernate/64: Mask off CR3's PCID bits in the saved CR3
Jiri reported a resume-from-hibernation failure triggered by PCID.
The root cause appears to be rather odd.  The hibernation asm
restores a CR3 value that comes from the image header.  If the image
kernel has PCID on, it's entirely reasonable for this CR3 value to
have one of the low 12 bits set.  The restore code restores it with
CR4.PCIDE=0, which means that those low 12 bits are accepted by the
CPU but are either ignored or interpreted as a caching mode.  This
is odd, but still works.  We blow up later when the image kernel
restores CR4, though, since changing CR4.PCIDE with CR3[11:0] != 0
is illegal.  Boom!

FWIW, it's entirely unclear to me what's supposed to happen if a PAE
kernel restores a non-PAE image or vice versa.  Ditto for LA57.

Reported-by: Jiri Kosina <jikos@kernel.org>
Tested-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bpetkov@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: 660da7c922 ("x86/mm: Enable CR4.PCIDE on supported systems")
Link: http://lkml.kernel.org/r/18ca57090651a6341e97083883f9e814c4f14684.1504847163.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-09-13 09:52:37 +02:00
..
cpu.c x86/mm: Reinitialize TLB state on hotplug and resume 2017-09-06 20:12:57 -07:00
hibernate_32.c x86/mm: Convert trivial cases of page table walk to 5-level paging 2017-03-14 08:45:08 +01:00
hibernate_64.c x86/hibernate/64: Mask off CR3's PCID bits in the saved CR3 2017-09-13 09:52:37 +02:00
hibernate_asm_32.S x86, gdt, hibernate: Store/load GDT for hibernate path. 2013-05-02 11:27:35 -07:00
hibernate_asm_64.S x86/power/64: Do not refer to __PAGE_OFFSET from assembly code 2016-08-03 01:35:38 +02:00
Makefile objtool, x86: Add several functions and files to the objtool whitelist 2017-06-30 10:19:19 +02:00