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707d33cb0b
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
35 lines
1015 B
C
35 lines
1015 B
C
/*
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* HiSilicon Clock and Reset Driver Header
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*
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* Copyright (c) 2016 HiSilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __HISI_CRG_H
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#define __HISI_CRG_H
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struct hisi_clock_data;
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struct hisi_reset_controller;
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struct hisi_crg_funcs {
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struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
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void (*unregister_clks)(struct platform_device *pdev);
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};
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struct hisi_crg_dev {
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struct hisi_clock_data *clk_data;
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struct hisi_reset_controller *rstc;
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const struct hisi_crg_funcs *funcs;
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};
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#endif /* __HISI_CRG_H */
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