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https://github.com/edk2-porting/linux-next.git
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a05ce88ab3
Replace several device node absolute path lookups in the mv64x60 bootwrapper code with lookups by compatible or device_type properties. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
582 lines
17 KiB
C
582 lines
17 KiB
C
/*
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* Marvell hostbridge routines
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*
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* Author: Mark A. Greer <source@mvista.com>
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*
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* 2004, 2005, 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <stdarg.h>
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#include <stddef.h>
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#include "types.h"
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#include "elf.h"
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#include "page.h"
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#include "string.h"
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#include "stdio.h"
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#include "io.h"
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#include "ops.h"
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#include "mv64x60.h"
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#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define MV64x60_CPU2MEM_WINDOWS 4
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#define MV64x60_CPU2MEM_0_BASE 0x0008
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#define MV64x60_CPU2MEM_0_SIZE 0x0010
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#define MV64x60_CPU2MEM_1_BASE 0x0208
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#define MV64x60_CPU2MEM_1_SIZE 0x0210
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#define MV64x60_CPU2MEM_2_BASE 0x0018
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#define MV64x60_CPU2MEM_2_SIZE 0x0020
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#define MV64x60_CPU2MEM_3_BASE 0x0218
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#define MV64x60_CPU2MEM_3_SIZE 0x0220
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#define MV64x60_ENET2MEM_BAR_ENABLE 0x2290
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#define MV64x60_ENET2MEM_0_BASE 0x2200
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#define MV64x60_ENET2MEM_0_SIZE 0x2204
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#define MV64x60_ENET2MEM_1_BASE 0x2208
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#define MV64x60_ENET2MEM_1_SIZE 0x220c
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#define MV64x60_ENET2MEM_2_BASE 0x2210
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#define MV64x60_ENET2MEM_2_SIZE 0x2214
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#define MV64x60_ENET2MEM_3_BASE 0x2218
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#define MV64x60_ENET2MEM_3_SIZE 0x221c
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#define MV64x60_ENET2MEM_4_BASE 0x2220
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#define MV64x60_ENET2MEM_4_SIZE 0x2224
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#define MV64x60_ENET2MEM_5_BASE 0x2228
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#define MV64x60_ENET2MEM_5_SIZE 0x222c
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#define MV64x60_ENET2MEM_ACC_PROT_0 0x2294
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#define MV64x60_ENET2MEM_ACC_PROT_1 0x2298
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#define MV64x60_ENET2MEM_ACC_PROT_2 0x229c
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#define MV64x60_MPSC2MEM_BAR_ENABLE 0xf250
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#define MV64x60_MPSC2MEM_0_BASE 0xf200
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#define MV64x60_MPSC2MEM_0_SIZE 0xf204
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#define MV64x60_MPSC2MEM_1_BASE 0xf208
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#define MV64x60_MPSC2MEM_1_SIZE 0xf20c
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#define MV64x60_MPSC2MEM_2_BASE 0xf210
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#define MV64x60_MPSC2MEM_2_SIZE 0xf214
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#define MV64x60_MPSC2MEM_3_BASE 0xf218
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#define MV64x60_MPSC2MEM_3_SIZE 0xf21c
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#define MV64x60_MPSC_0_REMAP 0xf240
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#define MV64x60_MPSC_1_REMAP 0xf244
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#define MV64x60_MPSC2MEM_ACC_PROT_0 0xf254
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#define MV64x60_MPSC2MEM_ACC_PROT_1 0xf258
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#define MV64x60_MPSC2REGS_BASE 0xf25c
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#define MV64x60_IDMA2MEM_BAR_ENABLE 0x0a80
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#define MV64x60_IDMA2MEM_0_BASE 0x0a00
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#define MV64x60_IDMA2MEM_0_SIZE 0x0a04
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#define MV64x60_IDMA2MEM_1_BASE 0x0a08
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#define MV64x60_IDMA2MEM_1_SIZE 0x0a0c
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#define MV64x60_IDMA2MEM_2_BASE 0x0a10
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#define MV64x60_IDMA2MEM_2_SIZE 0x0a14
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#define MV64x60_IDMA2MEM_3_BASE 0x0a18
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#define MV64x60_IDMA2MEM_3_SIZE 0x0a1c
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#define MV64x60_IDMA2MEM_4_BASE 0x0a20
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#define MV64x60_IDMA2MEM_4_SIZE 0x0a24
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#define MV64x60_IDMA2MEM_5_BASE 0x0a28
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#define MV64x60_IDMA2MEM_5_SIZE 0x0a2c
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#define MV64x60_IDMA2MEM_6_BASE 0x0a30
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#define MV64x60_IDMA2MEM_6_SIZE 0x0a34
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#define MV64x60_IDMA2MEM_7_BASE 0x0a38
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#define MV64x60_IDMA2MEM_7_SIZE 0x0a3c
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#define MV64x60_IDMA2MEM_ACC_PROT_0 0x0a70
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#define MV64x60_IDMA2MEM_ACC_PROT_1 0x0a74
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#define MV64x60_IDMA2MEM_ACC_PROT_2 0x0a78
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#define MV64x60_IDMA2MEM_ACC_PROT_3 0x0a7c
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#define MV64x60_PCI_ACC_CNTL_WINDOWS 6
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#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
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#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
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#define MV64x60_PCI0_BAR_ENABLE 0x0c3c
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#define MV64x60_PCI02MEM_0_SIZE 0x0c08
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#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
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#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
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#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
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#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
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#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
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#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
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#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
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#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
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#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
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#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
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#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
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#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
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#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
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#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
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#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
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#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
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#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
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#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
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#define MV64x60_PCI1_BAR_ENABLE 0x0cbc
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#define MV64x60_PCI12MEM_0_SIZE 0x0c88
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#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
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#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
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#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
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#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
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#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
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#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
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#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
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#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
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#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
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#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
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#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
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#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
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#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
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#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
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#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
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#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
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#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
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#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
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#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
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#define MV64x60_CPU2PCI0_IO_BASE 0x0048
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#define MV64x60_CPU2PCI0_IO_SIZE 0x0050
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#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
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#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
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#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
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#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
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#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
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#define MV64x60_CPU2PCI1_IO_BASE 0x0090
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#define MV64x60_CPU2PCI1_IO_SIZE 0x0098
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#define MV64x60_CPU2PCI1_IO_REMAP 0x0108
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#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
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#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
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#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
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#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
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struct mv64x60_mem_win {
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u32 hi;
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u32 lo;
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u32 size;
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};
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struct mv64x60_pci_win {
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u32 fcn;
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u32 hi;
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u32 lo;
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u32 size;
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};
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/* PCI config access routines */
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struct {
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u32 addr;
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u32 data;
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} static mv64x60_pci_cfgio[2] = {
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{ /* hose 0 */
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.addr = 0xcf8,
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.data = 0xcfc,
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},
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{ /* hose 1 */
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.addr = 0xc78,
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.data = 0xc7c,
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}
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};
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u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)
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{
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out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
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(1 << 31) | (bus << 16) | (devfn << 8) | offset);
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return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));
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}
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void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,
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u32 val)
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{
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out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
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(1 << 31) | (bus << 16) | (devfn << 8) | offset);
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out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);
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}
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/* I/O ctlr -> system memory setup */
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static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
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{
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.lo = MV64x60_CPU2MEM_0_BASE,
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.size = MV64x60_CPU2MEM_0_SIZE,
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},
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{
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.lo = MV64x60_CPU2MEM_1_BASE,
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.size = MV64x60_CPU2MEM_1_SIZE,
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},
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{
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.lo = MV64x60_CPU2MEM_2_BASE,
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.size = MV64x60_CPU2MEM_2_SIZE,
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},
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{
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.lo = MV64x60_CPU2MEM_3_BASE,
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.size = MV64x60_CPU2MEM_3_SIZE,
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},
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};
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static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = {
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{
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.lo = MV64x60_ENET2MEM_0_BASE,
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.size = MV64x60_ENET2MEM_0_SIZE,
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},
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{
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.lo = MV64x60_ENET2MEM_1_BASE,
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.size = MV64x60_ENET2MEM_1_SIZE,
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},
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{
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.lo = MV64x60_ENET2MEM_2_BASE,
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.size = MV64x60_ENET2MEM_2_SIZE,
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},
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{
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.lo = MV64x60_ENET2MEM_3_BASE,
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.size = MV64x60_ENET2MEM_3_SIZE,
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},
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};
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static struct mv64x60_mem_win mv64x60_mpsc2mem[MV64x60_CPU2MEM_WINDOWS] = {
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{
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.lo = MV64x60_MPSC2MEM_0_BASE,
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.size = MV64x60_MPSC2MEM_0_SIZE,
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},
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{
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.lo = MV64x60_MPSC2MEM_1_BASE,
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.size = MV64x60_MPSC2MEM_1_SIZE,
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},
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{
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.lo = MV64x60_MPSC2MEM_2_BASE,
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.size = MV64x60_MPSC2MEM_2_SIZE,
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},
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{
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.lo = MV64x60_MPSC2MEM_3_BASE,
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.size = MV64x60_MPSC2MEM_3_SIZE,
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},
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};
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static struct mv64x60_mem_win mv64x60_idma2mem[MV64x60_CPU2MEM_WINDOWS] = {
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{
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.lo = MV64x60_IDMA2MEM_0_BASE,
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.size = MV64x60_IDMA2MEM_0_SIZE,
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},
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{
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.lo = MV64x60_IDMA2MEM_1_BASE,
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.size = MV64x60_IDMA2MEM_1_SIZE,
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},
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{
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.lo = MV64x60_IDMA2MEM_2_BASE,
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.size = MV64x60_IDMA2MEM_2_SIZE,
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},
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{
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.lo = MV64x60_IDMA2MEM_3_BASE,
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.size = MV64x60_IDMA2MEM_3_SIZE,
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},
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};
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static u32 mv64x60_dram_selects[MV64x60_CPU2MEM_WINDOWS] = {0xe,0xd,0xb,0x7};
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/*
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* ENET, MPSC, and IDMA ctlrs on the MV64x60 have separate windows that
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* must be set up so that the respective ctlr can access system memory.
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* Configure them to be same as cpu->memory windows.
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*/
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void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
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u8 is_coherent)
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{
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u32 i, base, size, enables, prot = 0, snoop_bits = 0;
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/* Disable ctlr->mem windows */
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out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f);
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out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf);
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out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff);
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if (is_coherent)
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snoop_bits = 0x2 << 12; /* Writeback */
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enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
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for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
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if (enables & (1 << i)) /* Set means disabled */
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continue;
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base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))
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<< 16;
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base |= snoop_bits | (mv64x60_dram_selects[i] << 8);
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size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))
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<< 16;
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prot |= (0x3 << (i << 1)); /* RW access */
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out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base);
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out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size);
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out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base);
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out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size);
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out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base);
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out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size);
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}
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out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot);
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out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot);
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out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot);
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out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot);
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out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot);
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out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot);
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out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot);
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out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot);
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out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot);
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/* Set mpsc->bridge's reg window to the bridge's internal registers. */
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out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE),
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(u32)bridge_pbase);
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out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables);
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out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables);
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out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables);
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}
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/* PCI MEM -> system memory, et. al. setup */
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static struct mv64x60_pci_win mv64x60_pci2mem[2] = {
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{ /* hose 0 */
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.fcn = 0,
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.hi = 0x14,
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.lo = 0x10,
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.size = MV64x60_PCI02MEM_0_SIZE,
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},
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{ /* hose 1 */
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.fcn = 0,
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.hi = 0x94,
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.lo = 0x90,
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.size = MV64x60_PCI12MEM_0_SIZE,
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},
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};
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static struct
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mv64x60_mem_win mv64x60_pci_acc[2][MV64x60_PCI_ACC_CNTL_WINDOWS] = {
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{ /* hose 0 */
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{
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.hi = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
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.lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
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.size = MV64x60_PCI0_ACC_CNTL_0_SIZE,
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},
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{
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.hi = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
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.lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
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.size = MV64x60_PCI0_ACC_CNTL_1_SIZE,
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},
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{
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.hi = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
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.lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
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.size = MV64x60_PCI0_ACC_CNTL_2_SIZE,
|
|
},
|
|
{
|
|
.hi = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
|
|
.lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
|
|
.size = MV64x60_PCI0_ACC_CNTL_3_SIZE,
|
|
},
|
|
},
|
|
{ /* hose 1 */
|
|
{
|
|
.hi = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
|
|
.lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
|
|
.size = MV64x60_PCI1_ACC_CNTL_0_SIZE,
|
|
},
|
|
{
|
|
.hi = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
|
|
.lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
|
|
.size = MV64x60_PCI1_ACC_CNTL_1_SIZE,
|
|
},
|
|
{
|
|
.hi = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
|
|
.lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
|
|
.size = MV64x60_PCI1_ACC_CNTL_2_SIZE,
|
|
},
|
|
{
|
|
.hi = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
|
|
.lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
|
|
.size = MV64x60_PCI1_ACC_CNTL_3_SIZE,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct mv64x60_mem_win mv64x60_pci2reg[2] = {
|
|
{
|
|
.hi = 0x24,
|
|
.lo = 0x20,
|
|
.size = 0,
|
|
},
|
|
{
|
|
.hi = 0xa4,
|
|
.lo = 0xa0,
|
|
.size = 0,
|
|
},
|
|
};
|
|
|
|
/* Only need to use 1 window (per hose) to get access to all of system memory */
|
|
void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
|
|
u8 bus, u32 mem_size, u32 acc_bits)
|
|
{
|
|
u32 i, offset, bar_enable, enables;
|
|
|
|
/* Disable all windows but PCI MEM -> Bridge's regs window */
|
|
enables = ~(1 << 9);
|
|
bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE;
|
|
out_le32((u32 *)(bridge_base + bar_enable), enables);
|
|
|
|
for (i=0; i<MV64x60_PCI_ACC_CNTL_WINDOWS; i++)
|
|
out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);
|
|
|
|
/* If mem_size is 0, leave windows disabled */
|
|
if (mem_size == 0)
|
|
return;
|
|
|
|
/* Cause automatic updates of PCI remap regs */
|
|
offset = hose ?
|
|
MV64x60_PCI1_PCI_DECODE_CNTL : MV64x60_PCI0_PCI_DECODE_CNTL;
|
|
i = in_le32((u32 *)(bridge_base + offset));
|
|
out_le32((u32 *)(bridge_base + offset), i & ~0x1);
|
|
|
|
mem_size = (mem_size - 1) & 0xfffff000;
|
|
|
|
/* Map PCI MEM addr 0 -> System Mem addr 0 */
|
|
mv64x60_cfg_write(bridge_base, hose, bus,
|
|
PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
|
|
mv64x60_pci2mem[hose].hi, 0);
|
|
mv64x60_cfg_write(bridge_base, hose, bus,
|
|
PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
|
|
mv64x60_pci2mem[hose].lo, 0);
|
|
out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);
|
|
|
|
acc_bits |= MV64x60_PCI_ACC_CNTL_ENABLE;
|
|
out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);
|
|
out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);
|
|
out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);
|
|
|
|
/* Set PCI MEM->bridge's reg window to where they are in CPU mem map */
|
|
i = (u32)bridge_base;
|
|
i &= 0xffff0000;
|
|
i |= (0x2 << 1);
|
|
mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
|
|
mv64x60_pci2reg[hose].hi, 0);
|
|
mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
|
|
mv64x60_pci2reg[hose].lo, i);
|
|
|
|
enables &= ~0x1; /* Enable PCI MEM -> System Mem window 0 */
|
|
out_le32((u32 *)(bridge_base + bar_enable), enables);
|
|
}
|
|
|
|
/* CPU -> PCI I/O & MEM setup */
|
|
struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2] = {
|
|
{ /* hose 0 */
|
|
.lo = MV64x60_CPU2PCI0_IO_BASE,
|
|
.size = MV64x60_CPU2PCI0_IO_SIZE,
|
|
.remap_hi = 0,
|
|
.remap_lo = MV64x60_CPU2PCI0_IO_REMAP,
|
|
},
|
|
{ /* hose 1 */
|
|
.lo = MV64x60_CPU2PCI1_IO_BASE,
|
|
.size = MV64x60_CPU2PCI1_IO_SIZE,
|
|
.remap_hi = 0,
|
|
.remap_lo = MV64x60_CPU2PCI1_IO_REMAP,
|
|
},
|
|
};
|
|
|
|
struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2] = {
|
|
{ /* hose 0 */
|
|
.lo = MV64x60_CPU2PCI0_MEM_0_BASE,
|
|
.size = MV64x60_CPU2PCI0_MEM_0_SIZE,
|
|
.remap_hi = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
|
|
.remap_lo = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
|
|
},
|
|
{ /* hose 1 */
|
|
.lo = MV64x60_CPU2PCI1_MEM_0_BASE,
|
|
.size = MV64x60_CPU2PCI1_MEM_0_SIZE,
|
|
.remap_hi = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
|
|
.remap_lo = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
|
|
},
|
|
};
|
|
|
|
/* Only need to set up 1 window to pci mem space */
|
|
void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
|
|
u32 pci_base_lo, u32 cpu_base, u32 size,
|
|
struct mv64x60_cpu2pci_win *offset_tbl)
|
|
{
|
|
cpu_base >>= 16;
|
|
cpu_base |= MV64x60_CPU2PCI_SWAP_NONE;
|
|
out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);
|
|
|
|
if (offset_tbl[hose].remap_hi != 0)
|
|
out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),
|
|
pci_base_hi);
|
|
out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),
|
|
pci_base_lo >> 16);
|
|
|
|
size = (size - 1) >> 16;
|
|
out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
|
|
}
|
|
|
|
/* Read mem ctlr to get the amount of mem in system */
|
|
u32 mv64x60_get_mem_size(u8 *bridge_base)
|
|
{
|
|
u32 enables, i, v;
|
|
u32 mem = 0;
|
|
|
|
enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
|
|
|
|
for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
|
|
if (!(enables & (1<<i))) {
|
|
v = in_le32((u32*)(bridge_base
|
|
+ mv64x60_cpu2mem[i].size));
|
|
v = ((v & 0xffff) + 1) << 16;
|
|
mem += v;
|
|
}
|
|
|
|
return mem;
|
|
}
|
|
|
|
/* Get physical address of bridge's registers */
|
|
u8 *mv64x60_get_bridge_pbase(void)
|
|
{
|
|
u32 v[2];
|
|
void *devp;
|
|
|
|
devp = find_node_by_compatible(NULL, "marvell,mv64360");
|
|
if (devp == NULL)
|
|
goto err_out;
|
|
if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
|
|
goto err_out;
|
|
|
|
return (u8 *)v[0];
|
|
|
|
err_out:
|
|
return 0;
|
|
}
|
|
|
|
/* Get virtual address of bridge's registers */
|
|
u8 *mv64x60_get_bridge_base(void)
|
|
{
|
|
u32 v;
|
|
void *devp;
|
|
|
|
devp = find_node_by_compatible(NULL, "marvell,mv64360");
|
|
if (devp == NULL)
|
|
goto err_out;
|
|
if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
|
|
goto err_out;
|
|
|
|
return (u8 *)v;
|
|
|
|
err_out:
|
|
return 0;
|
|
}
|
|
|
|
u8 mv64x60_is_coherent(void)
|
|
{
|
|
u32 v;
|
|
void *devp;
|
|
|
|
devp = finddevice("/");
|
|
if (devp == NULL)
|
|
return 1; /* Assume coherency on */
|
|
|
|
if (getprop(devp, "coherency-off", &v, sizeof(v)) < 0)
|
|
return 1; /* Coherency on */
|
|
else
|
|
return 0;
|
|
}
|