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8c9e8b0a28
BCM6318 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <F.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
21 lines
539 B
C
21 lines
539 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __DT_BINDINGS_RESET_BCM6318_H
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#define __DT_BINDINGS_RESET_BCM6318_H
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#define BCM6318_RST_SPI 0
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#define BCM6318_RST_EPHY 1
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#define BCM6318_RST_SAR 2
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#define BCM6318_RST_ENETSW 3
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#define BCM6318_RST_USBD 4
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#define BCM6318_RST_USBH 5
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#define BCM6318_RST_PCIE_CORE 6
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#define BCM6318_RST_PCIE 7
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#define BCM6318_RST_PCIE_EXT 8
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#define BCM6318_RST_PCIE_HARD 9
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#define BCM6318_RST_ADSL 10
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#define BCM6318_RST_PHYMIPS 11
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#define BCM6318_RST_HOSTMIPS 12
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#endif /* __DT_BINDINGS_RESET_BCM6318_H */
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