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32104b29cd
It seems PA7200 processors also suppress traps on loads to %r0. This means we can prefetch for read on these cpus. Of course, we can't support prefetch for write, since that requires LOAD DOUBLEWORD which was added with PA2.0 Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
40 lines
995 B
C
40 lines
995 B
C
/*
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* include/asm-parisc/prefetch.h
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*
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* PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
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* In addition, many implementations do hardware prefetching of both
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* instructions and data.
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*
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* PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
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* to gr0 but not in a way that Linux can use. If the load would cause an
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* interruption (eg due to prefetching 0), it is suppressed on PA2.0
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* processors, but not on 7300LC.
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*
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*/
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#ifndef __ASM_PARISC_PREFETCH_H
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#define __ASM_PARISC_PREFETCH_H
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_PREFETCH
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#define ARCH_HAS_PREFETCH
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extern inline void prefetch(const void *addr)
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{
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__asm__("ldw 0(%0), %%r0" : : "r" (addr));
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}
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/* LDD is a PA2.0 addition. */
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#ifdef CONFIG_PA20
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#define ARCH_HAS_PREFETCHW
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extern inline void prefetchw(const void *addr)
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{
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__asm__("ldd 0(%0), %%r0" : : "r" (addr));
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}
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#endif /* CONFIG_PA20 */
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#endif /* CONFIG_PREFETCH */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PARISC_PROCESSOR_H */
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