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d0035c62d9
There are potential cases in the future where the IOMMU might be mapping smaller pages than the regular MMU is using. Keep the allocator working on MMU pagesizes, but the low-level mapping functions need to map more than one TCE entry per page to deal with this. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
65 lines
2.1 KiB
C
65 lines
2.1 KiB
C
/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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* Rewrite, cleanup:
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* Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_TCE_H
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#define _ASM_TCE_H
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/*
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* Tces come in two formats, one for the virtual bus and a different
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* format for PCI
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*/
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#define TCE_VB 0
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#define TCE_PCI 1
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/* TCE page size is 4096 bytes (1 << 12) */
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#define TCE_SHIFT 12
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#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
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#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
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/* tce_entry
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* Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
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* abstracted so layout is irrelevant.
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*/
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union tce_entry {
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unsigned long te_word;
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struct {
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unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
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unsigned int tb_rsvd :6;
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unsigned long tb_rpn :40; /* Real page number */
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unsigned int tb_valid :1; /* Tce is valid (vb only) */
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unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
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unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
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unsigned int tb_pciwr :1; /* Write allowed (pci only) */
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unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
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} te_bits;
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#define te_cacheBits te_bits.tb_cacheBits
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#define te_rpn te_bits.tb_rpn
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#define te_valid te_bits.tb_valid
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#define te_allio te_bits.tb_allio
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#define te_lpindex te_bits.tb_lpindex
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#define te_pciwr te_bits.tb_pciwr
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#define te_rdwr te_bits.tb_rdwr
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};
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#endif
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