Thomas Gleixner f207890481 x86/mm: Map cpu_entry_area at the same place on 4/5 level ... There is no reason for 4 and 5 level pagetables to have a different layout. It just makes determining vaddr_end for KASLR harder than necessary. Fixes: 92a0f81d89 ("x86/cpu_entry_area: Move it out of the fixmap") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Benjamin Gilbert <benjamin.gilbert@coreos.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: stable <stable@vger.kernel.org> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Garnier <thgarnie@google.com>, Cc: Alexander Kuleshov <kuleshovmail@gmail.com> Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801041320360.1771@nanos		2018-01-04 23:04:57 +01:00
..
5level-paging.txt	x86: Enable 5-level paging support via CONFIG_X86_5LEVEL=y	2017-07-21 10:05:19 +02:00
00-INDEX
boot-options.txt	x86/mce: Update bootlog description to reflect behavior on AMD	2017-06-14 07:32:10 +02:00
cpu-hotplug-spec
fake-numa-for-cpusets	Documenation: update cgroup's document path	2016-08-03 15:43:58 -06:00
machinecheck	x86/Documentation: Fix various typos in Documentation/x86/ files	2016-07-01 10:00:10 +02:00
mm.txt	x86/mm: Map cpu_entry_area at the same place on 4/5 level	2018-01-04 23:04:57 +01:00
uefi.txt