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1b93a71755
As for RETINSTR, LOADREGS is a left-over from the 26-bit days. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
135 lines
2.8 KiB
ArmAsm
135 lines
2.8 KiB
ArmAsm
/*
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* linux/arch/arm/lib/ll_char_wr.S
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*
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* Copyright (C) 1995, 1996 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Speedups & 1bpp code (C) 1996 Philip Blundell & Russell King.
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*
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* 10-04-96 RMK Various cleanups & reduced register usage.
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* 08-04-98 RMK Shifts re-ordered
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*/
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@ Regs: [] = corruptible
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@ {} = used
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@ () = do not use
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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LC0: .word LC0
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.word bytes_per_char_h
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.word video_size_row
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.word acorndata_8x8
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.word con_charconvtable
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/*
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* r0 = ptr
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* r1 = char
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* r2 = white
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*/
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ENTRY(ll_write_char)
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stmfd sp!, {r4 - r7, lr}
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@
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@ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
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@
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/*
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* calculate offset into character table
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*/
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mov r1, r1, lsl #3
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/*
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* calculate offset required for each row.
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*/
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adr ip, LC0
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ldmia ip, {r3, r4, r5, r6, lr}
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sub ip, ip, r3
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add r6, r6, ip
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add lr, lr, ip
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ldr r4, [r4, ip]
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ldr r5, [r5, ip]
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/*
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* Go to resolution-dependent routine...
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*/
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cmp r4, #4
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blt Lrow1bpp
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add r0, r0, r5, lsl #3 @ Move to bottom of character
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orr r1, r1, #7
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ldrb r7, [r6, r1]
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teq r4, #8
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beq Lrow8bpplp
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@
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@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
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@
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Lrow4bpplp:
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ldr r7, [lr, r7, lsl #2]
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mul r7, r2, r7
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sub r1, r1, #1 @ avoid using r7 directly after
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str r7, [r0, -r5]!
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ldrb r7, [r6, r1]
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ldr r7, [lr, r7, lsl #2]
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mul r7, r2, r7
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tst r1, #7 @ avoid using r7 directly after
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str r7, [r0, -r5]!
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subne r1, r1, #1
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ldrneb r7, [r6, r1]
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bne Lrow4bpplp
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ldmfd sp!, {r4 - r7, pc}
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@
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@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
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@
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Lrow8bpplp:
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mov ip, r7, lsr #4
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ldr ip, [lr, ip, lsl #2]
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mul r4, r2, ip
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and ip, r7, #15 @ avoid r4
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ldr ip, [lr, ip, lsl #2] @ avoid r4
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mul ip, r2, ip @ avoid r4
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sub r1, r1, #1 @ avoid ip
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sub r0, r0, r5 @ avoid ip
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stmia r0, {r4, ip}
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ldrb r7, [r6, r1]
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mov ip, r7, lsr #4
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ldr ip, [lr, ip, lsl #2]
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mul r4, r2, ip
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and ip, r7, #15 @ avoid r4
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ldr ip, [lr, ip, lsl #2] @ avoid r4
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mul ip, r2, ip @ avoid r4
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tst r1, #7 @ avoid ip
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sub r0, r0, r5 @ avoid ip
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stmia r0, {r4, ip}
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subne r1, r1, #1
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ldrneb r7, [r6, r1]
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bne Lrow8bpplp
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ldmfd sp!, {r4 - r7, pc}
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@
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@ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
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@
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Lrow1bpp:
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add r6, r6, r1
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ldmia r6, {r4, r7}
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strb r4, [r0], r5
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mov r4, r4, lsr #8
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strb r4, [r0], r5
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mov r4, r4, lsr #8
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strb r4, [r0], r5
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mov r4, r4, lsr #8
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strb r4, [r0], r5
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strb r7, [r0], r5
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mov r7, r7, lsr #8
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strb r7, [r0], r5
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mov r7, r7, lsr #8
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strb r7, [r0], r5
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mov r7, r7, lsr #8
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strb r7, [r0], r5
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ldmfd sp!, {r4 - r7, pc}
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.bss
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ENTRY(con_charconvtable)
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.space 1024
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