mirror of
https://github.com/edk2-porting/linux-next.git
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df3bc8bd8f
Signed-off-by: Chas Williams <chas@cmf.nrl.navy.mil> Signed-off-by: David S. Miller <davem@davemloft.net>
242 lines
9.7 KiB
C
242 lines
9.7 KiB
C
/*
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* drivers/atm/suni.h - S/UNI PHY driver
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*/
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/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
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#ifndef DRIVER_ATM_SUNI_H
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#define DRIVER_ATM_SUNI_H
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#include <linux/atmdev.h>
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#include <linux/atmioc.h>
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#include <linux/sonet.h>
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/* SUNI registers */
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#define SUNI_MRI 0x00 /* Master Reset and Identity / Load
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Meter */
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#define SUNI_MC 0x01 /* Master Configuration */
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#define SUNI_MIS 0x02 /* Master Interrupt Status */
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/* no 0x03 */
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#define SUNI_MCM 0x04 /* Master Clock Monitor */
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#define SUNI_MCT 0x05 /* Master Control */
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#define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */
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#define SUNI_CRCS 0x07 /* Clock Recovery Control and Status */
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/* 0x08-0x0F reserved */
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#define SUNI_RSOP_CIE 0x10 /* RSOP Control/Interrupt Enable */
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#define SUNI_RSOP_SIS 0x11 /* RSOP Status/Interrupt Status */
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#define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */
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#define SUNI_RSOP_SBM 0x13 /* RSOP Section BIP-8 MSB */
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#define SUNI_TSOP_CTRL 0x14 /* TSOP Control */
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#define SUNI_TSOP_DIAG 0x15 /* TSOP Diagnostic */
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/* 0x16-0x17 reserved */
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#define SUNI_RLOP_CS 0x18 /* RLOP Control/Status */
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#define SUNI_RLOP_IES 0x19 /* RLOP Interrupt Enable/Status */
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#define SUNI_RLOP_LBL 0x1A /* RLOP Line BIP-8/24 LSB */
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#define SUNI_RLOP_LB 0x1B /* RLOP Line BIP-8/24 */
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#define SUNI_RLOP_LBM 0x1C /* RLOP Line BIP-8/24 MSB */
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#define SUNI_RLOP_LFL 0x1D /* RLOP Line FEBE LSB */
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#define SUNI_RLOP_LF 0x1E /* RLOP Line FEBE */
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#define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */
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#define SUNI_TLOP_CTRL 0x20 /* TLOP Control */
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#define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */
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/* 0x22-0x27 reserved */
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#define SUNI_SSTB_CTRL 0x28
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#define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */
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#define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */
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/* 0x32 reserved */
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#define SUNI_RPOP_IE 0x33 /* RPOP Interrupt Enable */
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/* 0x34-0x36 reserved */
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#define SUNI_RPOP_PSL 0x37 /* RPOP Path Signal Label */
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#define SUNI_RPOP_PBL 0x38 /* RPOP Path BIP-8 LSB */
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#define SUNI_RPOP_PBM 0x39 /* RPOP Path BIP-8 MSB */
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#define SUNI_RPOP_PFL 0x3A /* RPOP Path FEBE LSB */
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#define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */
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/* 0x3C reserved */
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#define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */
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#define SUNI_RPOP_RC 0x3D /* RPOP Ring Control (PM5355) */
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/* 0x3E-0x3F reserved */
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#define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */
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#define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */
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/* 0x42-0x44 reserved */
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#define SUNI_TPOP_APL 0x45 /* TPOP Arbitrary Pointer LSB */
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#define SUNI_TPOP_APM 0x46 /* TPOP Arbitrary Pointer MSB */
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/* 0x47 reserved */
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#define SUNI_TPOP_PSL 0x48 /* TPOP Path Signal Label */
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#define SUNI_TPOP_PS 0x49 /* TPOP Path Status */
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/* 0x4A-0x4F reserved */
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#define SUNI_RACP_CS 0x50 /* RACP Control/Status */
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#define SUNI_RACP_IES 0x51 /* RACP Interrupt Enable/Status */
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#define SUNI_RACP_MHP 0x52 /* RACP Match Header Pattern */
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#define SUNI_RACP_MHM 0x53 /* RACP Match Header Mask */
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#define SUNI_RACP_CHEC 0x54 /* RACP Correctable HCS Error Count */
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#define SUNI_RACP_UHEC 0x55 /* RACP Uncorrectable HCS Err Count */
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#define SUNI_RACP_RCCL 0x56 /* RACP Receive Cell Counter LSB */
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#define SUNI_RACP_RCC 0x57 /* RACP Receive Cell Counter */
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#define SUNI_RACP_RCCM 0x58 /* RACP Receive Cell Counter MSB */
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#define SUNI_RACP_CFG 0x59 /* RACP Configuration */
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/* 0x5A-0x5F reserved */
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#define SUNI_TACP_CS 0x60 /* TACP Control/Status */
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#define SUNI_TACP_IUCHP 0x61 /* TACP Idle/Unassigned Cell Hdr Pat */
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#define SUNI_TACP_IUCPOP 0x62 /* TACP Idle/Unassigned Cell Payload
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Octet Pattern */
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#define SUNI_TACP_FIFO 0x63 /* TACP FIFO Configuration */
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#define SUNI_TACP_TCCL 0x64 /* TACP Transmit Cell Counter LSB */
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#define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */
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#define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */
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#define SUNI_TACP_CFG 0x67 /* TACP Configuration */
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#define SUNI_SPTB_CTRL 0x68 /* SPTB Control */
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/* 0x69-0x7F reserved */
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#define SUNI_MT 0x80 /* Master Test */
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/* 0x81-0xFF reserved */
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/* SUNI register values */
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/* MRI is reg 0 */
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#define SUNI_MRI_ID 0x0f /* R, SUNI revision number */
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#define SUNI_MRI_ID_SHIFT 0
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#define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */
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#define SUNI_MRI_TYPE_SHIFT 4
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#define SUNI_MRI_TYPE_PM5346 0x3 /* S/UNI 155 LITE */
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#define SUNI_MRI_TYPE_PM5347 0x4 /* S/UNI 155 PLUS */
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#define SUNI_MRI_TYPE_PM5350 0x7 /* S/UNI 155 ULTRA */
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#define SUNI_MRI_TYPE_PM5355 0x1 /* S/UNI 622 */
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#define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip
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0: normal operation
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1: reset & low power */
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/* MCM is reg 0x4 */
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#define SUNI_MCM_LLE 0x20 /* line loopback (PM5355) */
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#define SUNI_MCM_DLE 0x10 /* diagnostic loopback (PM5355) */
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/* MCT is reg 5 */
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#define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from
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TRCLK+/- */
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#define SUNI_MCT_DLE 0x02 /* RW, diagnostic loopback */
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#define SUNI_MCT_LLE 0x04 /* RW, line loopback */
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#define SUNI_MCT_FIXPTR 0x20 /* RW, disable transmit payload pointer
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adjustments
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0: payload ptr controlled by TPOP
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ptr control reg
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1: payload pointer fixed at 522 */
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#define SUNI_MCT_LCDV 0x40 /* R, loss of cell delineation */
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#define SUNI_MCT_LCDE 0x80 /* RW, loss of cell delineation
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interrupt (1: on) */
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/* RSOP_CIE is reg 0x10 */
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#define SUNI_RSOP_CIE_OOFE 0x01 /* RW, enable interrupt on frame alarm
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state change */
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#define SUNI_RSOP_CIE_LOFE 0x02 /* RW, enable interrupt on loss of
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frame state change */
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#define SUNI_RSOP_CIE_LOSE 0x04 /* RW, enable interrupt on loss of
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signal state change */
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#define SUNI_RSOP_CIE_BIPEE 0x08 /* RW, enable interrupt on section
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BIP-8 error (B1) */
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#define SUNI_RSOP_CIE_FOOF 0x20 /* W, force RSOP out of frame at next
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boundary */
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#define SUNI_RSOP_CIE_DDS 0x40 /* RW, disable scrambling */
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/* RSOP_SIS is reg 0x11 */
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#define SUNI_RSOP_SIS_OOFV 0x01 /* R, out of frame */
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#define SUNI_RSOP_SIS_LOFV 0x02 /* R, loss of frame */
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#define SUNI_RSOP_SIS_LOSV 0x04 /* R, loss of signal */
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#define SUNI_RSOP_SIS_OOFI 0x08 /* R, out of frame interrupt */
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#define SUNI_RSOP_SIS_LOFI 0x10 /* R, loss of frame interrupt */
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#define SUNI_RSOP_SIS_LOSI 0x20 /* R, loss of signal interrupt */
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#define SUNI_RSOP_SIS_BIPEI 0x40 /* R, section BIP-8 interrupt */
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/* TSOP_CTRL is reg 0x14 */
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#define SUNI_TSOP_CTRL_LAIS 0x01 /* insert alarm indication signal */
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#define SUNI_TSOP_CTRL_DS 0x40 /* disable scrambling */
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/* TSOP_DIAG is reg 0x15 */
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#define SUNI_TSOP_DIAG_DFP 0x01 /* insert single bit error cont. */
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#define SUNI_TSOP_DIAG_DBIP8 0x02 /* insert section BIP err (cont) */
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#define SUNI_TSOP_DIAG_DLOS 0x04 /* set line to zero (loss of signal) */
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/* TLOP_DIAG is reg 0x21 */
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#define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */
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/* SSTB_CTRL is reg 0x28 */
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#define SUNI_SSTB_CTRL_LEN16 0x01 /* path trace message length bit */
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/* RPOP_RC is reg 0x3D (PM5355) */
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#define SUNI_RPOP_RC_ENSS 0x40 /* enable size bit */
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/* TPOP_DIAG is reg 0x40 */
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#define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */
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#define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */
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/* TPOP_APM is reg 0x46 */
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#define SUNI_TPOP_APM_APTR 0x03 /* RW, arbitrary pointer, upper 2
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bits */
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#define SUNI_TPOP_APM_APTR_SHIFT 0
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#define SUNI_TPOP_APM_S 0x0c /* RW, "unused" bits of payload
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pointer */
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#define SUNI_TPOP_APM_S_SHIFT 2
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#define SUNI_TPOP_APM_NDF 0xf0 /* RW, NDF bits */
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#define SUNI_TPOP_APM_NDF_SHIFT 4
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#define SUNI_TPOP_S_SONET 0 /* set S bits to 00 */
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#define SUNI_TPOP_S_SDH 2 /* set S bits to 10 */
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/* RACP_IES is reg 0x51 */
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#define SUNI_RACP_IES_FOVRI 0x02 /* R, FIFO overrun */
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#define SUNI_RACP_IES_UHCSI 0x04 /* R, uncorrectable HCS error */
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#define SUNI_RACP_IES_CHCSI 0x08 /* R, correctable HCS error */
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#define SUNI_RACP_IES_OOCDI 0x10 /* R, change of cell delineation
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state */
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#define SUNI_RACP_IES_FIFOE 0x20 /* RW, enable FIFO overrun interrupt */
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#define SUNI_RACP_IES_HCSE 0x40 /* RW, enable HCS error interrupt */
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#define SUNI_RACP_IES_OOCDE 0x80 /* RW, enable cell delineation state
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change interrupt */
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/* TACP_CS is reg 0x60 */
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#define SUNI_TACP_CS_FIFORST 0x01 /* RW, reset transmit FIFO (sticky) */
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#define SUNI_TACP_CS_DSCR 0x02 /* RW, disable payload scrambling */
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#define SUNI_TACP_CS_HCAADD 0x04 /* RW, add coset polynomial to HCS */
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#define SUNI_TACP_CS_DHCS 0x10 /* RW, insert HCS errors */
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#define SUNI_TACP_CS_FOVRI 0x20 /* R, FIFO overrun */
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#define SUNI_TACP_CS_TSOCI 0x40 /* R, TSOC input high */
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#define SUNI_TACP_CS_FIFOE 0x80 /* RW, enable FIFO overrun interrupt */
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/* TACP_IUCHP is reg 0x61 */
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#define SUNI_TACP_IUCHP_CLP 0x01 /* RW, 8th bit of 4th octet of i/u
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pattern */
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#define SUNI_TACP_IUCHP_PTI 0x0e /* RW, 5th-7th bits of 4th octet of i/u
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pattern */
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#define SUNI_TACP_IUCHP_PTI_SHIFT 1
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#define SUNI_TACP_IUCHP_GFC 0xf0 /* RW, 1st-4th bits of 1st octet of i/u
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pattern */
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#define SUNI_TACP_IUCHP_GFC_SHIFT 4
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/* SPTB_CTRL is reg 0x68 */
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#define SUNI_SPTB_CTRL_LEN16 0x01 /* path trace message length */
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/* MT is reg 0x80 */
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#define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface
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tri-state */
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#define SUNI_MT_HIZDATA 0x02 /* W, also tri-state data bus */
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#define SUNI_MT_IOTST 0x04 /* RW, enable test mode */
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#define SUNI_MT_DBCTRL 0x08 /* W, control data bus by CSB pin */
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#define SUNI_MT_PMCTST 0x10 /* W, PMC test mode */
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#define SUNI_MT_DS27_53 0x80 /* RW, select between 8- or 16- bit */
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#define SUNI_IDLE_PATTERN 0x6a /* idle pattern */
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#ifdef __KERNEL__
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struct suni_priv {
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struct k_sonet_stats sonet_stats; /* link diagnostics */
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int loop_mode; /* loopback mode */
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int type; /* phy type */
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struct atm_dev *dev; /* device back-pointer */
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struct suni_priv *next; /* next SUNI */
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};
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int suni_init(struct atm_dev *dev);
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#endif
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#endif
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