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b4f173752a
Tegra20 HW appears to have a bug such that PCIe device interrupts, whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around this, simply disable LP2 if any PCIe devices with interrupts are present. Detect this via the IRQ domain map operation. This is slightly over-conservative; if a device with an interrupt is present but the driver does not actually use them, LP2 will still be disabled. However, this is a reasonable trade-off which enables a simpler workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
230 lines
5.1 KiB
C
230 lines
5.1 KiB
C
/*
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* CPU idle driver for Tegra CPUs
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*
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* Copyright (c) 2010-2012, NVIDIA Corporation.
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* Copyright (c) 2011 Google, Inc.
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* Author: Colin Cross <ccross@android.com>
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* Gary King <gking@nvidia.com>
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*
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* Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/clockchips.h>
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#include <linux/clk/tegra.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include <asm/smp_plat.h>
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#include "pm.h"
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#include "sleep.h"
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#include "iomap.h"
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#include "irq.h"
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#include "flowctrl.h"
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#ifdef CONFIG_PM_SLEEP
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static bool abort_flag;
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static atomic_t abort_barrier;
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static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index);
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#define TEGRA20_MAX_STATES 2
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#else
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#define TEGRA20_MAX_STATES 1
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#endif
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static struct cpuidle_driver tegra_idle_driver = {
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.name = "tegra_idle",
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.owner = THIS_MODULE,
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.states = {
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ARM_CPUIDLE_WFI_STATE_PWR(600),
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#ifdef CONFIG_PM_SLEEP
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{
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.enter = tegra20_idle_lp2_coupled,
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.exit_latency = 5000,
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.target_residency = 10000,
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.power_usage = 0,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_COUPLED,
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.name = "powered-down",
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.desc = "CPU power gated",
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},
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#endif
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},
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.state_count = TEGRA20_MAX_STATES,
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.safe_state_index = 0,
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};
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_SMP
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static int tegra20_reset_sleeping_cpu_1(void)
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{
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int ret = 0;
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tegra_pen_lock();
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if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
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tegra20_cpu_shutdown(1);
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else
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ret = -EINVAL;
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tegra_pen_unlock();
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return ret;
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}
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static void tegra20_wake_cpu1_from_reset(void)
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{
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tegra_pen_lock();
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tegra20_cpu_clear_resettable();
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/* enable cpu clock on cpu */
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tegra_enable_cpu_clock(1);
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/* take the CPU out of reset */
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tegra_cpu_out_of_reset(1);
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/* unhalt the cpu */
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flowctrl_write_cpu_halt(1, 0);
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tegra_pen_unlock();
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}
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static int tegra20_reset_cpu_1(void)
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{
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if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
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return 0;
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tegra20_wake_cpu1_from_reset();
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return -EBUSY;
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}
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#else
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static inline void tegra20_wake_cpu1_from_reset(void)
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{
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}
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static inline int tegra20_reset_cpu_1(void)
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{
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return 0;
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}
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#endif
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static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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while (tegra20_cpu_is_resettable_soon())
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cpu_relax();
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if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
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return false;
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
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tegra_idle_lp2_last();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
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if (cpu_online(1))
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tegra20_wake_cpu1_from_reset();
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return true;
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}
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#ifdef CONFIG_SMP
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static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
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cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
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tegra20_cpu_clear_resettable();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
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return true;
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}
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#else
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static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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return true;
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}
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#endif
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static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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bool entered_lp2 = false;
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if (tegra_pending_sgi())
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ACCESS_ONCE(abort_flag) = true;
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cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
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if (abort_flag) {
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cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
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abort_flag = false; /* clean flag for next coming */
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return -EINTR;
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}
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local_fiq_disable();
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tegra_set_cpu_in_lp2();
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cpu_pm_enter();
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if (dev->cpu == 0)
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entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
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else
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entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
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cpu_pm_exit();
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tegra_clear_cpu_in_lp2();
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local_fiq_enable();
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smp_rmb();
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return entered_lp2 ? index : 0;
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}
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#endif
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/*
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* Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
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* they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
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* this, simply disable LP2 if the PCI driver and DT node are both enabled.
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*/
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void tegra20_cpuidle_pcie_irqs_in_use(void)
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{
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pr_info_once(
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"Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
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tegra_idle_driver.states[1].disabled = true;
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}
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int __init tegra20_cpuidle_init(void)
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{
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return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
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}
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