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387f0de6c3
On Rockchip I2C the controller drops SDA low slightly too soon to meet the "repeated start" requirements. >From my own experimentation over a number of rates: - controller appears to drop SDA at .875x (7/8) programmed clk high. - controller appears to keep SCL high for 2x programmed clk high. The first rule isn't enough to meet tSU;STA requirements in Standard-mode on the system I tested on. The second rule is probably enough to meet tHD;STA requirements in nearly all cases (especially after accounting for the first), but it doesn't hurt to account for it anyway just in case. Even though the repeated start requirement only need to be accounted for during a small part of the transfer, we'll adjust the timings for the whole transfer to meet it. I believe that adjusting the timings in just the right place to switch things up for repeated start would require several extra interrupts and that doesn't seem terribly worth it. With this change and worst case rise/fall times, I see 100kHz i2c going to ~85kHz. With slightly optimized rise/fall (800ns / 50ns) I see i2c going to ~89kHz. Fast-mode isn't affected much because tSU;STA is shorter relative to tHD;STA there. As part of this change we needed to account for the SDA falling time. The specification indicates that this should be the same, but we'll follow Designware's lead and add a binding. Note that we deviate from Designware and assign the default SDA falling time to be the same as the SCL falling time, which is incredibly likely. Signed-off-by: Doug Anderson <dianders@chromium.org> [wsa: rebased to i2c/for-next] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
57 lines
1.7 KiB
Plaintext
57 lines
1.7 KiB
Plaintext
* Rockchip RK3xxx I2C controller
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This driver interfaces with the native I2C controller present in Rockchip
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RK3xxx SoCs.
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Required properties :
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- reg : Offset and length of the register set for the device
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- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
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"rockchip,rk3288-i2c".
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- interrupts : interrupt number
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- clocks : parent clock
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Required on RK3066, RK3188 :
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- rockchip,grf : the phandle of the syscon node for the general register
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file (GRF)
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- on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF)
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is also required.
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Optional properties :
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- clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
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- i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise
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(t(r) in I2C specification). If not specified this is assumed to be
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the maximum the specification allows(1000 ns for Standard-mode,
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300 ns for Fast-mode) which might cause slightly slower communication.
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- i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall
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(t(f) in the I2C specification). If not specified this is assumed to
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be the maximum the specification allows (300 ns) which might cause
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slightly slower communication.
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- i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall
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(t(f) in the I2C specification). If not specified we'll use the SCL
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value since they are the same in nearly all cases.
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Example:
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aliases {
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i2c0 = &i2c0;
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}
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i2c0: i2c@2002d000 {
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compatible = "rockchip,rk3188-i2c";
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reg = <0x2002d000 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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i2c-scl-rising-time-ns = <800>;
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i2c-scl-falling-time-ns = <100>;
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};
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