mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 14:14:01 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
92 lines
1.9 KiB
C
92 lines
1.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 2001 Keith M Wesolowski
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/pci.h>
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#include <asm/ip32/mace.h>
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#if 0
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# define DPRINTK(args...) printk(args);
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#else
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# define DPRINTK(args...)
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#endif
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/*
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* O2 has up to 5 PCI devices connected into the MACE bridge. The device
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* map looks like this:
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*
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* 0 aic7xxx 0
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* 1 aic7xxx 1
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* 2 expansion slot
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* 3 N/C
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* 4 N/C
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*/
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#define chkslot(_bus,_devfn) \
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do { \
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if ((_bus)->number > 0 || PCI_SLOT (_devfn) < 1 \
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|| PCI_SLOT (_devfn) > 3) \
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return PCIBIOS_DEVICE_NOT_FOUND; \
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} while (0)
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#define mkaddr(_devfn, _reg) \
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((((_devfn) & 0xffUL) << 8) | ((_reg) & 0xfcUL))
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static int
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mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 *val)
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{
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chkslot(bus, devfn);
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mace->pci.config_addr = mkaddr(devfn, reg);
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switch (size) {
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case 1:
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*val = mace->pci.config_data.b[(reg & 3) ^ 3];
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break;
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case 2:
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*val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
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break;
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case 4:
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*val = mace->pci.config_data.l;
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break;
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}
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DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int reg, int size, u32 val)
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{
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chkslot(bus, devfn);
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mace->pci.config_addr = mkaddr(devfn, reg);
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switch (size) {
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case 1:
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mace->pci.config_data.b[(reg & 3) ^ 3] = val;
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break;
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case 2:
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mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
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break;
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case 4:
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mace->pci.config_data.l = val;
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break;
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}
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DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops mace_pci_ops = {
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.read = mace_pci_read_config,
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.write = mace_pci_write_config,
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};
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