mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 13:13:57 +08:00
f0157b3afd
F11h has almost the same MCE signatures as K8 except DRAM ECC and MC5 bank errors. Reuse functionality from the other families. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
669 lines
13 KiB
C
669 lines
13 KiB
C
#include <linux/module.h>
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#include <linux/slab.h>
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#include "mce_amd.h"
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static struct amd_decoder_ops *fam_ops;
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static u8 nb_err_cpumask = 0xf;
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
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{
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nb_bus_decoder = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
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{
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if (nb_bus_decoder) {
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WARN_ON(nb_bus_decoder != f);
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nb_bus_decoder = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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*/
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/* transaction type */
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const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
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EXPORT_SYMBOL_GPL(tt_msgs);
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/* cache level */
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const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
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EXPORT_SYMBOL_GPL(ll_msgs);
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/* memory transaction type */
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const char *rrrr_msgs[] = {
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"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
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};
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EXPORT_SYMBOL_GPL(rrrr_msgs);
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/* participating processor */
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const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
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EXPORT_SYMBOL_GPL(pp_msgs);
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/* request timeout */
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const char *to_msgs[] = { "no timeout", "timed out" };
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EXPORT_SYMBOL_GPL(to_msgs);
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/* memory or i/o */
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const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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EXPORT_SYMBOL_GPL(ii_msgs);
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static const char *f10h_nb_mce_desc[] = {
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"HT link data error",
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"Protocol error (link, L3, probe filter, etc.)",
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"Parity error in NB-internal arrays",
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"Link Retry due to IO link transmission error",
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"L3 ECC data cache error",
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"ECC error in L3 cache tag",
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"L3 LRU parity bits error",
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"ECC Error in the Probe Filter directory"
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};
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static bool f10h_dc_mce(u16 ec)
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{
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u8 r4 = (ec >> 4) & 0xf;
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bool ret = false;
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if (r4 == R4_GEN) {
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pr_cont("during data scrub.\n");
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return true;
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}
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if (MEM_ERROR(ec)) {
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u8 ll = ec & 0x3;
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ret = true;
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if (ll == LL_L2)
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pr_cont("during L1 linefill from L2.\n");
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else if (ll == LL_L1)
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pr_cont("Data/Tag %s error.\n", RRRR_MSG(ec));
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else
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ret = false;
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}
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return ret;
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}
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static bool k8_dc_mce(u16 ec)
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{
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if (BUS_ERROR(ec)) {
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pr_cont("during system linefill.\n");
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return true;
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}
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return f10h_dc_mce(ec);
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}
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static bool f14h_dc_mce(u16 ec)
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{
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u8 r4 = (ec >> 4) & 0xf;
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u8 ll = ec & 0x3;
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u8 tt = (ec >> 2) & 0x3;
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u8 ii = tt;
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bool ret = true;
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if (MEM_ERROR(ec)) {
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if (tt != TT_DATA || ll != LL_L1)
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return false;
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switch (r4) {
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case R4_DRD:
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case R4_DWR:
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pr_cont("Data/Tag parity error due to %s.\n",
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(r4 == R4_DRD ? "load/hw prf" : "store"));
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break;
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case R4_EVICT:
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pr_cont("Copyback parity error on a tag miss.\n");
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break;
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case R4_SNOOP:
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pr_cont("Tag parity error during snoop.\n");
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break;
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default:
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ret = false;
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}
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} else if (BUS_ERROR(ec)) {
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if ((ii != II_MEM && ii != II_IO) || ll != LL_LG)
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return false;
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pr_cont("System read data error on a ");
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switch (r4) {
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case R4_RD:
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pr_cont("TLB reload.\n");
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break;
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case R4_DWR:
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pr_cont("store.\n");
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break;
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case R4_DRD:
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pr_cont("load.\n");
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break;
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default:
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ret = false;
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}
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} else {
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ret = false;
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}
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return ret;
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}
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static void amd_decode_dc_mce(struct mce *m)
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{
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u16 ec = m->status & 0xffff;
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u8 xec = (m->status >> 16) & 0xf;
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pr_emerg(HW_ERR "Data Cache Error: ");
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/* TLB error signatures are the same across families */
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if (TLB_ERROR(ec)) {
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u8 tt = (ec >> 2) & 0x3;
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if (tt == TT_DATA) {
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pr_cont("%s TLB %s.\n", LL_MSG(ec),
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(xec ? "multimatch" : "parity error"));
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return;
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}
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else
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goto wrong_dc_mce;
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}
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if (!fam_ops->dc_mce(ec))
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goto wrong_dc_mce;
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return;
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wrong_dc_mce:
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pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
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}
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static bool k8_ic_mce(u16 ec)
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{
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u8 ll = ec & 0x3;
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u8 r4 = (ec >> 4) & 0xf;
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bool ret = true;
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if (!MEM_ERROR(ec))
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return false;
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if (ll == 0x2)
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pr_cont("during a linefill from L2.\n");
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else if (ll == 0x1) {
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switch (r4) {
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case R4_IRD:
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pr_cont("Parity error during data load.\n");
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break;
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case R4_EVICT:
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pr_cont("Copyback Parity/Victim error.\n");
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break;
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case R4_SNOOP:
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pr_cont("Tag Snoop error.\n");
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break;
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default:
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ret = false;
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break;
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}
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} else
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ret = false;
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return ret;
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}
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static bool f14h_ic_mce(u16 ec)
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{
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u8 ll = ec & 0x3;
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u8 tt = (ec >> 2) & 0x3;
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u8 r4 = (ec >> 4) & 0xf;
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bool ret = true;
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if (MEM_ERROR(ec)) {
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if (tt != 0 || ll != 1)
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ret = false;
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if (r4 == R4_IRD)
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pr_cont("Data/tag array parity error for a tag hit.\n");
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else if (r4 == R4_SNOOP)
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pr_cont("Tag error during snoop/victimization.\n");
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else
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ret = false;
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}
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return ret;
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}
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static void amd_decode_ic_mce(struct mce *m)
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{
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u16 ec = m->status & 0xffff;
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u8 xec = (m->status >> 16) & 0xf;
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pr_emerg(HW_ERR "Instruction Cache Error: ");
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if (TLB_ERROR(ec))
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pr_cont("%s TLB %s.\n", LL_MSG(ec),
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(xec ? "multimatch" : "parity error"));
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else if (BUS_ERROR(ec)) {
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bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT(58)));
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pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
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} else if (fam_ops->ic_mce(ec))
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;
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else
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pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
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}
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static void amd_decode_bu_mce(struct mce *m)
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{
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u32 ec = m->status & 0xffff;
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u32 xec = (m->status >> 16) & 0xf;
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pr_emerg(HW_ERR "Bus Unit Error");
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if (xec == 0x1)
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pr_cont(" in the write data buffers.\n");
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else if (xec == 0x3)
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pr_cont(" in the victim data buffers.\n");
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else if (xec == 0x2 && MEM_ERROR(ec))
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pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
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else if (xec == 0x0) {
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if (TLB_ERROR(ec))
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pr_cont(": %s error in a Page Descriptor Cache or "
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"Guest TLB.\n", TT_MSG(ec));
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else if (BUS_ERROR(ec))
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pr_cont(": %s/ECC error in data read from NB: %s.\n",
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RRRR_MSG(ec), PP_MSG(ec));
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else if (MEM_ERROR(ec)) {
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u8 rrrr = (ec >> 4) & 0xf;
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if (rrrr >= 0x7)
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pr_cont(": %s error during data copyback.\n",
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RRRR_MSG(ec));
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else if (rrrr <= 0x1)
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pr_cont(": %s parity/ECC error during data "
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"access from L2.\n", RRRR_MSG(ec));
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else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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return;
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wrong_bu_mce:
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pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
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}
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static void amd_decode_ls_mce(struct mce *m)
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{
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u16 ec = m->status & 0xffff;
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u8 xec = (m->status >> 16) & 0xf;
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if (boot_cpu_data.x86 == 0x14) {
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pr_emerg("You shouldn't be seeing an LS MCE on this cpu family,"
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" please report on LKML.\n");
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return;
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}
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pr_emerg(HW_ERR "Load Store Error");
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if (xec == 0x0) {
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u8 r4 = (ec >> 4) & 0xf;
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if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
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goto wrong_ls_mce;
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pr_cont(" during %s.\n", RRRR_MSG(ec));
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} else
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goto wrong_ls_mce;
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return;
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wrong_ls_mce:
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pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
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}
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static bool k8_nb_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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switch (xec) {
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case 0x1:
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pr_cont("CRC error detected on HT link.\n");
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break;
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case 0x5:
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pr_cont("Invalid GART PTE entry during GART table walk.\n");
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break;
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case 0x6:
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pr_cont("Unsupported atomic RMW received from an IO link.\n");
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break;
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case 0x0:
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case 0x8:
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if (boot_cpu_data.x86 == 0x11)
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return false;
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pr_cont("DRAM ECC error detected on the NB.\n");
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break;
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case 0xd:
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pr_cont("Parity error on the DRAM addr/ctl signals.\n");
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break;
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default:
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ret = false;
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break;
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}
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return ret;
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}
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static bool f10h_nb_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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u8 offset = 0;
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if (k8_nb_mce(ec, xec))
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return true;
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switch(xec) {
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case 0xa ... 0xc:
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offset = 10;
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break;
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case 0xe:
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offset = 11;
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break;
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case 0xf:
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if (TLB_ERROR(ec))
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pr_cont("GART Table Walk data error.\n");
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else if (BUS_ERROR(ec))
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pr_cont("DMA Exclusion Vector Table Walk error.\n");
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else
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ret = false;
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goto out;
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break;
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case 0x1c ... 0x1f:
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offset = 24;
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break;
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default:
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ret = false;
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goto out;
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break;
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}
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pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
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out:
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return ret;
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}
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static bool f14h_nb_mce(u16 ec, u8 xec)
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{
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return false;
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}
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void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
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{
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u8 xec = (m->status >> 16) & 0x1f;
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u16 ec = m->status & 0xffff;
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u32 nbsh = (u32)(m->status >> 32);
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pr_emerg(HW_ERR "Northbridge Error, node %d: ", node_id);
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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* value encoding has changed so interpret those differently
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*/
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 7)) {
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if (nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u", (u8)(nbsh & nb_err_cpumask));
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} else {
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u8 assoc_cpus = nbsh & nb_err_cpumask;
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if (assoc_cpus > 0)
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pr_cont(", core: %d", fls(assoc_cpus) - 1);
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}
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switch (xec) {
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case 0x2:
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pr_cont("Sync error (sync packets on HT link detected).\n");
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return;
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case 0x3:
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pr_cont("HT Master abort.\n");
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return;
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case 0x4:
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pr_cont("HT Target abort.\n");
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return;
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case 0x7:
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pr_cont("NB Watchdog timeout.\n");
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return;
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case 0x9:
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pr_cont("SVM DMA Exclusion Vector error.\n");
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return;
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default:
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break;
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}
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if (!fam_ops->nb_mce(ec, xec))
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goto wrong_nb_mce;
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
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if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
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nb_bus_decoder(node_id, m, nbcfg);
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return;
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wrong_nb_mce:
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pr_emerg(HW_ERR "Corrupted NB MCE info?\n");
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}
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EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
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static void amd_decode_fr_mce(struct mce *m)
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{
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if (boot_cpu_data.x86 == 0xf ||
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boot_cpu_data.x86 == 0x11)
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goto wrong_fr_mce;
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/* we have only one error signature so match all fields at once. */
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if ((m->status & 0xffff) == 0x0f0f) {
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pr_emerg(HW_ERR "FR Error: CPU Watchdog timer expire.\n");
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return;
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}
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wrong_fr_mce:
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pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
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}
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static inline void amd_decode_err_code(u16 ec)
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{
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if (TLB_ERROR(ec)) {
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pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, "
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"Participating Processor: %s\n",
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RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
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PP_MSG(ec));
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} else
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pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
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}
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/*
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* Filter out unwanted MCE signatures here.
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*/
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static bool amd_filter_mce(struct mce *m)
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{
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u8 xec = (m->status >> 16) & 0x1f;
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|
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/*
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* NB GART TLB error reporting is disabled by default.
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*/
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if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
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return true;
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return false;
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}
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|
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int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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{
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struct mce *m = (struct mce *)data;
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int node, ecc;
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|
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if (amd_filter_mce(m))
|
|
return NOTIFY_STOP;
|
|
|
|
pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);
|
|
|
|
pr_cont("%sorrected error, other errors lost: %s, "
|
|
"CPU context corrupt: %s",
|
|
((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
|
|
((m->status & MCI_STATUS_OVER) ? "yes" : "no"),
|
|
((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
|
|
|
|
/* do the two bits[14:13] together */
|
|
ecc = (m->status >> 45) & 0x3;
|
|
if (ecc)
|
|
pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
|
|
|
|
pr_cont("\n");
|
|
|
|
switch (m->bank) {
|
|
case 0:
|
|
amd_decode_dc_mce(m);
|
|
break;
|
|
|
|
case 1:
|
|
amd_decode_ic_mce(m);
|
|
break;
|
|
|
|
case 2:
|
|
amd_decode_bu_mce(m);
|
|
break;
|
|
|
|
case 3:
|
|
amd_decode_ls_mce(m);
|
|
break;
|
|
|
|
case 4:
|
|
node = amd_get_nb_id(m->extcpu);
|
|
amd_decode_nb_mce(node, m, 0);
|
|
break;
|
|
|
|
case 5:
|
|
amd_decode_fr_mce(m);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
amd_decode_err_code(m->status & 0xffff);
|
|
|
|
return NOTIFY_STOP;
|
|
}
|
|
EXPORT_SYMBOL_GPL(amd_decode_mce);
|
|
|
|
static struct notifier_block amd_mce_dec_nb = {
|
|
.notifier_call = amd_decode_mce,
|
|
};
|
|
|
|
static int __init mce_amd_init(void)
|
|
{
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
|
|
return 0;
|
|
|
|
if ((boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) &&
|
|
(boot_cpu_data.x86 != 0x14 || boot_cpu_data.x86_model > 0xf))
|
|
return 0;
|
|
|
|
fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
|
|
if (!fam_ops)
|
|
return -ENOMEM;
|
|
|
|
switch (boot_cpu_data.x86) {
|
|
case 0xf:
|
|
fam_ops->dc_mce = k8_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = k8_nb_mce;
|
|
break;
|
|
|
|
case 0x10:
|
|
fam_ops->dc_mce = f10h_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = f10h_nb_mce;
|
|
break;
|
|
|
|
case 0x11:
|
|
fam_ops->dc_mce = k8_dc_mce;
|
|
fam_ops->ic_mce = k8_ic_mce;
|
|
fam_ops->nb_mce = f10h_nb_mce;
|
|
break;
|
|
|
|
case 0x14:
|
|
nb_err_cpumask = 0x3;
|
|
fam_ops->dc_mce = f14h_dc_mce;
|
|
fam_ops->ic_mce = f14h_ic_mce;
|
|
fam_ops->nb_mce = f14h_nb_mce;
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_WARNING "Huh? What family is that: %d?!\n",
|
|
boot_cpu_data.x86);
|
|
kfree(fam_ops);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pr_info("MCE: In-kernel MCE decoding enabled.\n");
|
|
|
|
atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(mce_amd_init);
|
|
|
|
#ifdef MODULE
|
|
static void __exit mce_amd_exit(void)
|
|
{
|
|
atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
|
|
kfree(fam_ops);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("AMD MCE decoder");
|
|
MODULE_ALIAS("edac-mce-amd");
|
|
MODULE_LICENSE("GPL");
|
|
module_exit(mce_amd_exit);
|
|
#endif
|