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9169b51f8c
This patch makes sure to sync the pipeline for the root stage only from the outer interrupt level, when resuming kernel code after an interrupt. This fixes a bug causing EVT15 to be spuriously popped off upon nested interrupts, which in turn would cause the preempted kernel code to resume without supervisor privileges. Signed-off-by: Philippe Gerum <rpm@xenomai.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
327 lines
7.1 KiB
ArmAsm
327 lines
7.1 KiB
ArmAsm
/*
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* Interrupt Entries
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*
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* Copyright 2005-2009 Analog Devices Inc.
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* D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>
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* Kenneth Albanowski <kjahds@kjahds.com>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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#include <mach/irq.h>
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#include <linux/linkage.h>
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#include <asm/entry.h>
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#include <asm/asm-offsets.h>
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#include <asm/trace.h>
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#include <asm/traps.h>
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#include <asm/thread_info.h>
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#include <asm/context.S>
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.extern _ret_from_exception
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#ifdef CONFIG_I_ENTRY_L1
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.section .l1.text
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#else
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.text
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#endif
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.align 4 /* just in case */
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/* Common interrupt entry code. First we do CLI, then push
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* RETI, to keep interrupts disabled, but to allow this state to be changed
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* by local_bh_enable.
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* R0 contains the interrupt number, while R1 may contain the value of IPEND,
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* or garbage if IPEND won't be needed by the ISR. */
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__common_int_entry:
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[--sp] = fp;
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[--sp] = usp;
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[--sp] = i0;
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[--sp] = i1;
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[--sp] = i2;
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[--sp] = i3;
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[--sp] = m0;
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[--sp] = m1;
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[--sp] = m2;
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[--sp] = m3;
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[--sp] = l0;
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[--sp] = l1;
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[--sp] = l2;
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[--sp] = l3;
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[--sp] = b0;
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[--sp] = b1;
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[--sp] = b2;
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[--sp] = b3;
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[--sp] = a0.x;
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[--sp] = a0.w;
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[--sp] = a1.x;
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[--sp] = a1.w;
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[--sp] = LC0;
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[--sp] = LC1;
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[--sp] = LT0;
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[--sp] = LT1;
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[--sp] = LB0;
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[--sp] = LB1;
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[--sp] = ASTAT;
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[--sp] = r0; /* Skip reserved */
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[--sp] = RETS;
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r2 = RETI;
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[--sp] = r2;
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[--sp] = RETX;
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[--sp] = RETN;
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[--sp] = RETE;
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[--sp] = SEQSTAT;
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[--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
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/* Switch to other method of keeping interrupts disabled. */
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#ifdef CONFIG_DEBUG_HWERR
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r1 = 0x3f;
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sti r1;
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#else
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cli r1;
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#endif
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#ifdef CONFIG_TRACE_IRQFLAGS
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[--sp] = r0;
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sp += -12;
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call _trace_hardirqs_off;
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sp += 12;
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r0 = [sp++];
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#endif
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[--sp] = RETI; /* orig_pc */
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/* Clear all L registers. */
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r1 = 0 (x);
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l0 = r1;
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l1 = r1;
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l2 = r1;
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l3 = r1;
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#ifdef CONFIG_FRAME_POINTER
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fp = 0;
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#endif
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ANOMALY_283_315_WORKAROUND(p5, r7)
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r1 = sp;
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SP += -12;
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#ifdef CONFIG_IPIPE
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call ___ipipe_grab_irq
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SP += 12;
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cc = r0 == 0;
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if cc jump .Lcommon_restore_context;
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#else /* CONFIG_IPIPE */
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#ifdef CONFIG_PREEMPT
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r7 = sp;
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r4.l = lo(ALIGN_PAGE_MASK);
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r4.h = hi(ALIGN_PAGE_MASK);
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r7 = r7 & r4;
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p5 = r7;
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r7 = [p5 + TI_PREEMPT]; /* get preempt count */
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r7 += 1; /* increment it */
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[p5 + TI_PREEMPT] = r7;
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#endif
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pseudo_long_call _do_irq, p2;
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#ifdef CONFIG_PREEMPT
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r7 += -1;
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[p5 + TI_PREEMPT] = r7; /* restore preempt count */
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#endif
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SP += 12;
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#endif /* CONFIG_IPIPE */
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pseudo_long_call _return_from_int, p2;
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.Lcommon_restore_context:
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RESTORE_CONTEXT
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rti;
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/* interrupt routine for ivhw - 5 */
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ENTRY(_evt_ivhw)
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/* In case a single action kicks off multiple memory transactions, (like
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* a cache line fetch, - this can cause multiple hardware errors, let's
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* catch them all. First - make sure all the actions are complete, and
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* the core sees the hardware errors.
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*/
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SSYNC;
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SSYNC;
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SAVE_ALL_SYS
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#ifdef CONFIG_FRAME_POINTER
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fp = 0;
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#endif
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ANOMALY_283_315_WORKAROUND(p5, r7)
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/* Handle all stacked hardware errors
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* To make sure we don't hang forever, only do it 10 times
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*/
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R0 = 0;
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R2 = 10;
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1:
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P0.L = LO(ILAT);
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P0.H = HI(ILAT);
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R1 = [P0];
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CC = BITTST(R1, EVT_IVHW_P);
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IF ! CC JUMP 2f;
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/* OK a hardware error is pending - clear it */
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R1 = EVT_IVHW_P;
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[P0] = R1;
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R0 += 1;
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CC = R1 == R2;
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if CC JUMP 2f;
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JUMP 1b;
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2:
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# We are going to dump something out, so make sure we print IPEND properly
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p2.l = lo(IPEND);
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p2.h = hi(IPEND);
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r0 = [p2];
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[sp + PT_IPEND] = r0;
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/* set the EXCAUSE to HWERR for trap_c */
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r0 = [sp + PT_SEQSTAT];
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R1.L = LO(VEC_HWERR);
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R1.H = HI(VEC_HWERR);
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R0 = R0 | R1;
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[sp + PT_SEQSTAT] = R0;
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r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
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SP += -12;
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pseudo_long_call _trap_c, p5;
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SP += 12;
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#ifdef EBIU_ERRMST
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/* make sure EBIU_ERRMST is clear */
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p0.l = LO(EBIU_ERRMST);
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p0.h = HI(EBIU_ERRMST);
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r0.l = (CORE_ERROR | CORE_MERROR);
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w[p0] = r0.l;
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#endif
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pseudo_long_call _ret_from_exception, p2;
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.Lcommon_restore_all_sys:
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RESTORE_ALL_SYS
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rti;
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ENDPROC(_evt_ivhw)
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/* Interrupt routine for evt2 (NMI).
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* For inner circle type details, please see:
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* http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi
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*/
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ENTRY(_evt_nmi)
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#ifndef CONFIG_NMI_WATCHDOG
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.weak _evt_nmi
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#else
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/* Not take account of CPLBs, this handler will not return */
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SAVE_ALL_SYS
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r0 = sp;
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r1 = retn;
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[sp + PT_PC] = r1;
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trace_buffer_save(p4,r5);
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ANOMALY_283_315_WORKAROUND(p4, r5)
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SP += -12;
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call _do_nmi;
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SP += 12;
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1:
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jump 1b;
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#endif
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rtn;
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ENDPROC(_evt_nmi)
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/* interrupt routine for core timer - 6 */
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ENTRY(_evt_timer)
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TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P)
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/* interrupt routine for evt7 - 7 */
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ENTRY(_evt_evt7)
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INTERRUPT_ENTRY(EVT_IVG7_P)
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ENTRY(_evt_evt8)
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INTERRUPT_ENTRY(EVT_IVG8_P)
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ENTRY(_evt_evt9)
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INTERRUPT_ENTRY(EVT_IVG9_P)
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ENTRY(_evt_evt10)
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INTERRUPT_ENTRY(EVT_IVG10_P)
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ENTRY(_evt_evt11)
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INTERRUPT_ENTRY(EVT_IVG11_P)
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ENTRY(_evt_evt12)
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INTERRUPT_ENTRY(EVT_IVG12_P)
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ENTRY(_evt_evt13)
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INTERRUPT_ENTRY(EVT_IVG13_P)
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/* interrupt routine for system_call - 15 */
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ENTRY(_evt_system_call)
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SAVE_CONTEXT_SYSCALL
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#ifdef CONFIG_FRAME_POINTER
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fp = 0;
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#endif
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pseudo_long_call _system_call, p2;
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jump .Lcommon_restore_context;
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ENDPROC(_evt_system_call)
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#ifdef CONFIG_IPIPE
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/*
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* __ipipe_call_irqtail: lowers the current priority level to EVT15
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* before running a user-defined routine, then raises the priority
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* level to EVT14 to prepare the caller for a normal interrupt
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* return through RTI.
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*
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* We currently use this feature in two occasions:
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*
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* - before branching to __ipipe_irq_tail_hook as requested by a high
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* priority domain after the pipeline delivered an interrupt,
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* e.g. such as Xenomai, in order to start its rescheduling
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* procedure, since we may not switch tasks when IRQ levels are
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* nested on the Blackfin, so we have to fake an interrupt return
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* so that we may reschedule immediately.
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*
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* - before branching to __ipipe_sync_root(), in order to play any interrupt
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* pending for the root domain (i.e. the Linux kernel). This lowers
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* the core priority level enough so that Linux IRQ handlers may
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* never delay interrupts handled by high priority domains; we defer
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* those handlers until this point instead. This is a substitute
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* to using a threaded interrupt model for the Linux kernel.
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*
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* r0: address of user-defined routine
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* context: caller must have preempted EVT15, hw interrupts must be off.
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*/
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ENTRY(___ipipe_call_irqtail)
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p0 = r0;
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r0.l = 1f;
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r0.h = 1f;
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reti = r0;
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rti;
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1:
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[--sp] = rets;
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[--sp] = ( r7:4, p5:3 );
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sp += -12;
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call (p0);
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sp += 12;
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( r7:4, p5:3 ) = [sp++];
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rets = [sp++];
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#ifdef CONFIG_DEBUG_HWERR
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/* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
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r0 = (EVT_IVG14 | EVT_IVHW | \
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EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
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#else
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/* Only enable irq14 interrupt, until we transition to _evt_evt14 */
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r0 = (EVT_IVG14 | \
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EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
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#endif
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sti r0;
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raise 14; /* Branches to _evt_evt14 */
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2:
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jump 2b; /* Likely paranoid. */
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ENDPROC(___ipipe_call_irqtail)
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#endif /* CONFIG_IPIPE */
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