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7d4c2af9bd
The ath79_device_reset_* are causing BUG when those are used on the QCA955x SoCs. The patch adds the required code to avoid that. Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com> Cc: Giori, Kathy <kgiori@qca.qualcomm.com> Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4948/ Signed-off-by: John Crispin <blogic@openwrt.org>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X common routines
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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static DEFINE_SPINLOCK(ath79_device_reset_lock);
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u32 ath79_cpu_freq;
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EXPORT_SYMBOL_GPL(ath79_cpu_freq);
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u32 ath79_ahb_freq;
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EXPORT_SYMBOL_GPL(ath79_ahb_freq);
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u32 ath79_ddr_freq;
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EXPORT_SYMBOL_GPL(ath79_ddr_freq);
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enum ath79_soc_type ath79_soc;
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unsigned int ath79_soc_rev;
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void __iomem *ath79_pll_base;
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void __iomem *ath79_reset_base;
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EXPORT_SYMBOL_GPL(ath79_reset_base);
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void __iomem *ath79_ddr_base;
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void ath79_ddr_wb_flush(u32 reg)
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{
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void __iomem *flush_reg = ath79_ddr_base + reg;
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/* Flush the DDR write buffer. */
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__raw_writel(0x1, flush_reg);
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while (__raw_readl(flush_reg) & 0x1)
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;
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/* It must be run twice. */
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__raw_writel(0x1, flush_reg);
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while (__raw_readl(flush_reg) & 0x1)
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;
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}
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EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
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void ath79_device_reset_set(u32 mask)
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{
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unsigned long flags;
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u32 reg;
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u32 t;
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if (soc_is_ar71xx())
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reg = AR71XX_RESET_REG_RESET_MODULE;
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else if (soc_is_ar724x())
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reg = AR724X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar913x())
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reg = AR913X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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BUG();
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spin_lock_irqsave(&ath79_device_reset_lock, flags);
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t = ath79_reset_rr(reg);
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ath79_reset_wr(reg, t | mask);
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spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ath79_device_reset_set);
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void ath79_device_reset_clear(u32 mask)
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{
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unsigned long flags;
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u32 reg;
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u32 t;
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if (soc_is_ar71xx())
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reg = AR71XX_RESET_REG_RESET_MODULE;
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else if (soc_is_ar724x())
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reg = AR724X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar913x())
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reg = AR913X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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BUG();
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spin_lock_irqsave(&ath79_device_reset_lock, flags);
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t = ath79_reset_rr(reg);
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ath79_reset_wr(reg, t & ~mask);
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spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
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}
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EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
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